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TPS731 PMOS Equivalent

Amanda Ross95
Intellectual 2740 points
Other Parts Discussed in Thread: TPS799, TLV713, TPS731

Hello there,

I've been trying to spec an equivalent to the TPS73101 but I can't find anything that is cap-free (found the TPS799 and I'm wondering if that's the best option). Would you be able to help me identify the closest thing you have to it but in a PMOS configuration?

Vin = 4.6V - 5V,

Vout = 4.5V,

Iout = 100-150mA

Any suggestions you have would be helpful.

Thanks,

-Amanda

  • 0
    TI__Guru 50040 points

    Hi Amanda,

    The only 150mA device I know of with a P-Channel FET is the TLV713. However, it can not handle a 4.5V output.

    Why are you looking for a P-Channel vs N-Channel solution? If I understand the application and load, maybe I can suggest something.

    Regards,

  • 0 in reply to JCHK
    TI__Intellectual 2740 points
    Hello John,

    The customer was having troubles with the TPS73101 and found an excerpt from its datasheet which reads “approximately –0.2 V of VOUT results in a current limit of 0 mA. Therefore, if OUT is forced below –0.2 V before EN goes high, the device may not start up.” They're wondering if the TPS731 not starting is possibly a consequence of the relationship between the the short circuit current and the output voltage. So based on that, they're thinking a PMOS based LDO may be the answer.

    I referred them to the TPS799 and they said that may work but they would like to know if there is a minimum impedance that the FB pin requires on either fixed or adjustable versions?

    Let me know if you have any other suggestions or if we're maybe heading down the wrong road. Thank you so much for your time!

    -Amanda
  • 0 in reply to Amanda Ross95
    TI__Guru 50040 points

    HI Amanda,

    The TPS799 is a simpler part (i.e. no charge pump) so may have an easier time starting even if VOUT is negative. As for the FB resistor recommendation, the key concern is the input leakage into or out of the FB pin Maximum rating of  +/-0.5uA so as long as the FB current VOUT/(R1+R2) is much larger than 0.5uA, there will not be a huge impact on accuracy. These are CMOS inputs so theoretically the leakage in or out is 0 but over process and temperature there is concern that there could be some leakage which is why we have the min/max value on the datasheet.

    So the smaller you make R1+R2, the better the performance would be but at the expense of increased leakage on the output. The datasheet is a bit light on recommending the resistors, but the EVM has a series resistance of ~400K .


    I hope this helps.

  • 0 in reply to JCHK
    TI__Intellectual 2740 points

    Thanks so much John for your help and your detailed answer. It's always a pleasure when the individuals on the forum explain things in a way that allows us in the field to better understand the behaviors and inner workings of the device as well. Your time is very appreciated.

    Best Regards,
    -Amanda

  • 0 in reply to Amanda Ross95
    TI__Guru 50040 points
    Hi Amanda,

    Thank you. I am glad I could help.

    Regards,