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about bq76pl455 balance function

feimy chen
Prodigy 90 points
Other Parts Discussed in Thread: BQ76PL455A

hello

Here are some questions about pl455's balance function  want to consult you

1、the cell's voltage will be changed when i turn  on the balanced switch  and  there was a beat voltage with 5mV ~ 20mV  on the next battary?

for example

the cell n's normal volt is  3450mv ,the cell n's volt will be  up to about 3456 ~3460mv  when i turn on EQ(n-1)   

why so?

2、It's about  the "TSCONFIG"   reg address is 0x1E,  the  BIT5 (EQ_SQUEEZE_EN) can not be written 1 ,I want to test the open wire detection funciton

and so how can I write the 1 to it ?

3、The power of VIOREG ,can be use to the VIO in single mode?

  • 0
    TI__Intellectual 2795 points

    Hi Feimy,

    To answer your questions:

    1. If there is a shared connection to the cell for both VSENSE and balancing, then this is expected. The balance current will cause an offset due to the current over the shared path of the cell connection (on-board traces, connector and wire harness).
    2. How are you writing it to 1, and how are you checking if it written? If you are doing this from the register view in the GUI, then you need to read the register after writing to refresh the view.
    3. VIO-REG is intended to supply the VIO input when the single-ended interface is not used. In single-ended mode (UART connected to host) VIO must be supplied from the IOVCC of the MCU or the same supply used for the RX signal.

    Regards,

    Stephen

  • 0 in reply to Stephen Holland
    Prodigy 90 points
    hi here is an another question

    pl455s are working in the daisy chain mode ,the bottom IC's power would be closed when turned off VCC , But the others are still working
    and so ,how can i shut down power of the second board or follow boards ?
  • 0 in reply to feimy chen
    TI__Genius 10785 points
    Basically, you send broadcast command to power down.
    Or, you can set comm time on every slave ICs.
    You can find the more details in the datasheet section 7.4.1 Shutdown.
    I can explain in detail if needed.
  • 0 in reply to Stephen Holland
    Prodigy 90 points
    hi Stepphen

    1、Should I use two wires for a battery cell,one is for sample and the other for balance?
    2、I have sent the single mode type and written 0x18 to it, I read the registor back ,return data 's length is right but value was always 0, use SCI
    program as follow
    byte bTemp[2] ={0};
    bTemp[0] = 0x10; bTemp[1] = 0;
    bFg = Pl455WriteCmd(bAddress,0x1E,bTemp,2,SIG_WRT_NONE_RESP); //single write with none resp
    bTemp[0] = 0x01;bTemp[1] = 0;
    bFg = Pl455WriteCmd(bAddress,0x1e,bTemp,1,SIG_WRT_WITH_RESP); //single write with resp
    bFg = Pl455ReadData(bTemp,5);
  • 0 in reply to feimy chen
    TI__Genius 11480 points
    Hello Chen,

    On our EVM, we use only the one wire, but I don't see why there would be problems if you wanted to use two wires.

    Could you clarify what you are trying to do with the code?

    writing 0x1000 to the TSTCONFIG register (0x1E) is writing to a reserved bit, which I would recommend against doing.
    writing 0x0100 to the TSTCONFIG register is setting the LDO_TEST[0] bit to 1, and info on this test is minimal in the datasheet.


    If you are trying to implement OWD, you could:

    Set the CBCONFIG[BAL_Continue] to 1
    Write 0x0010 to the TSTCONFIG register (eq_squeeze_enable =1), and please read section 7.3.12.8.1 of the datasheet for more info
    then, use the CBENBL register to control the squeeze resistors.
  • 0 in reply to David Wiest Jr
    Prodigy 90 points
    sorry
    many days ago ,i have asked some question about pl455
    questions as follow
    1、the cell's voltage will be changed when i turn on the balanced switch and there was a beat voltage with 5mV ~ 20mV on the next battary?
    for example
    the cell n's normal volt is 3450mv ,the cell n's volt will be up to about 3456 ~3460mv when i turn on EQ(n-1)
    why so?
    2、It's about the "TSCONFIG" reg address is 0x1E, the BIT5 (EQ_SQUEEZE_EN) can not be written 1 ,I want to test the open wire detection funciton
    and so how can I write the 1 to it ?

    and then Stephen answered:

    If there is a shared connection to the cell for both VSENSE and balancing, then this is expected. The balance current will cause an offset due to the current over the shared path of the cell connection (on-board traces, connector and wire harness).
    How are you writing it to 1, and how are you checking if it written? If you are doing this from the register view in the GUI, then you need to read the register after writing to refresh the view.


    so my question s

    1、Should I use two wires for a battery cell,one is for sample and the other for balance?
    2、I have sent the single mode type and written 0x18 to it, I read the registor back ,return data 's length is right but value was always 0, use SCI
    program as follow
    byte bTemp[2] ={0};
    bTemp[0] = 0x10; bTemp[1] = 0;
    bFg = Pl455WriteCmd(bAddress,0x1E,bTemp,2,SIG_WRT_NONE_RESP); //single write with none resp
    bTemp[0] = 0x01;bTemp[1] = 0;
    bFg = Pl455WriteCmd(bAddress,0x1e,bTemp,1,SIG_WRT_WITH_RESP); //single write with resp
    bFg = Pl455ReadData(bTemp,5);
  • 0 in reply to feimy chen
    TI__Intellectual 2795 points

    Hi Chen,

    I will try to answer your questions:

    1. You can, but most do not as this will now mean double the number of connector pins and wires to connect the cells. These connectors and wires are very expensive. It is expected (just ohm's law) that there will be an offset due to the balance current over the shared connection, so it usually just compensated for in the MCU algorithm.
    2. The API looks OK, but we can't know how your functions work without having the complete code. We have provided example C code here. I would suggest reviewing our code to see if it matches what you have implemented.
      1. It would be better to provide exactly what the UART frame being generated by your code is. This way we can see if your code is working correctly or not. Please also specify the register address you are trying to read.

    Regards,

    Stephen

  • 0 in reply to Stephen Holland
    Prodigy 90 points

    hi Stephen
    thank you for your reply!
    you may be did not see what i had said
    i think the balancing is abnormal,because the cell voltage will be up when i start the bancing and voltage will be abnormal when i stop balancing,
    for example the 3th cell's normal volt is 3340mV,and the fourth cell's volt is 3300;when i start the balancing for the 3th cell,and the fourth cell's volt will be high(3350mv) ;but the fourth cell 's volt will be ok(3300mV) when stop balancing ;and the sampled data is wrong when balancing
    so How can I solve this problem?  start the balancing ,i would never be able to find  the max cell or min cell 

    and then
    maybe i have known why "TSCONFIG" can't be written 1,
    i should be wrong about the data send order , bTemp[0] = 0x10; bTemp[1] = 0; must be changed to bTemp[0] = 0x0;0 bTemp[1] = 0x10;
    the high 8 bits is sent first, how do you think?

  • 0 in reply to feimy chen
    TI__Intellectual 2795 points

    Hi Chen,

    What you are seeing is simply from ohm's law. I have created a drawing below to try to explain why you are seeing the extra offset on the adjacent channel. It is expected, and can in fact be calculated in your code to remove the offset if necessary. The current is known (balance current = measured cell voltage before balancing / sum of balance resistor and EQ FET Rdson. Your cell connection harness and connector contact impedance x the balance current is the source of the offset.

    Regards,

    Stephen

  • 0 in reply to Stephen Holland
    Prodigy 90 points
    hi Stephen
    turn on EQ2 as your drawing ,Bat3 is +35mV not -35mV on my side,and so this is my question . and bat2 less than -35mv is normal,
    maybe you knew the solution of LTC 6804 , 6804 was normal when started balanceing. it was no problems at not

    ps:
    i have a new problem ,
    when I disconnected one of the acquisition line , and the corresponding voltage was not be changed , the value get form pl455 is normal,in fact the volt is 0V.,how can i do it ?
  • 0 in reply to feimy chen
    TI__Genius 11480 points
    Hi Chen,

    Stephen is out of office, so I will try to help you.

    I believe that there is a small understanding with regards to your first question. With Stephens explanation, Bat3 would measure +35mV higher than before. The voltage measurement is differential, so moving the bottom reference down would increase the overall voltage reading.

    If I am understanding the new issue correctly,you remove a cell and the pl455 reads that the cell you removed is 0V? Or does it maintain the cell voltage?
  • 0 in reply to feimy chen
    Prodigy 90 points
    hi David:

    I want to konw how can i do to solve the problem about question one ?if acquisition and balanceing must be done at the same time
    Normally,we will choose the cell which is the highest voltage to discharge with resistance, but the position of cell which is the highest voltage will be changed when i begin balanceing

    the new issue is Similar to that We still can collect to the normal voltage when a cell is open wire ,the voltage value is not changed

    understand?
  • 0 in reply to feimy chen
    TI__Genius 11480 points
    Hi Chen,

    As Stephen mentioned in a previous post, this offset is something that can be calculated in your firmware. In the code, you can then do something along the lines of:

    Vcell(actual) = Vcell-Voffset

    in your code. You would use that formula only when measuring the cells you are balancing, and a normal formula all other times.


    With regards to the new issue, it is expected. The capacitor in the low pass filter will maintain that voltage, since only it will only see large impedances to ground. If you enable charging on the cell you remove, you would see the voltage drop quickly as the capacitor is discharged. Alternatively, you could enable the squeeze resistor to discharge the capacitor.
  • 0 in reply to David Wiest Jr
    Prodigy 90 points

    hi David
    That is right you explained, but how can i detect the cell open wire whether or not.

    do you have detail method to get open wire infomation.?

    thank you 

  • 0 in reply to feimy chen
    TI__Genius 11480 points

    Hi Chen,

    With  the current  setup, you would know that the  cell has been  removed because the capacitor would discharge with  the squeeze resistor. If a  cell is in place, you would effectively  just be loading the cell and  the  voltage would stay relatively close to  what it was before.

    For  detailed descriptions  of  the 455 safety diagnostic tests, you would  have  to refer to the  bq76PL455A Safety Manual. We do require an  NDA  be  in place before  disclosing the  455  safety information.... does  your  company have one  in place  with TI?

  • 0 in reply to David Wiest Jr
    Prodigy 90 points

    hi David

    I implement owd follow your steps ,

    but ,how can i know ,which cell was open wire?we just set the register value,and control the owd action ,

    so i want to know the conditions of judgment about which is open wire

  • 0 in reply to feimy chen
    TI__Genius 11480 points
    Hi Feimy,

    you should do an adc reading before OWD, and some time after (time depends on your judgement). If the voltage has not changed (except offsets due to IR drop), then the wire is connected. If the capacitor has discharged some, the wire is open