Hi Sir,
1. May I know Frequency-Jitter tolerance about UCC28700? example fs equal 60kHz.
2. May I know Duty Ton control method about UCC28700? Depend on what condition?
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Hi Kuo,
The internal timing control of the UCC28700 gate is proprietary information, but it follows the scheme which I described in my previous reply. The switching frequency and gate on time are set according to the Vcl voltage in the Control Law (Figure 15, page 14 of the datasheet). The nominal switching frequency is set by the Vcl. The gate-drive is turned on long enough for primary peak current Ipp to reach the level determined by Vcl, then is turned off. The level of Ipp is sensed at the CS input. The error voltage Vcl is a function of the output power level. Higher load results in higher Vcl, high frequency and high Ipp. Low load results in low Vcl, low frequency and low Ipp.
This file illustrates the EMI jittering scheme implemented in the UCC28700 device family. EMI Jitter - UCC28700.pdf The actual cycle-by-cycle jittering is modified by additional disturbances such as valley switching, load perturbations and noise, so the observed jitter may deviate considerably from the ideal pattern described.
Regards,
Ulrich
Hi Sir,
1. Check with waveform, VCS occur other spike when output voltage drop.
May I know this spike can affect out controller error?
2. May I know after what long Blacking Time UCC28700 into valley switch ?
Vin : 115Vac, Vout : 5V / 3.4A
CH1 : Vaux, CH2 : Vcs, CH4 : Vout
3. Ripple carrier 3kHz noise is right?
Hi Kuo, it looks like some noise is being injected onto the Aux winding which is causing an increase in the winding voltage at the instant that it is sampled to determine the output voltage. This makes the output voltage look too high to the controller and it therefore decreases the switching frequency and peak current.
Is the flyback operating in a system with other switching stages? Is there something else which could be injecting noise into the aux signal?
Thanks
Billy