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LM3630A - About minimum dimming PWM duty cycle and Flicker

Hide
Guru 21045 points
Other Parts Discussed in Thread: LM3630A, LM3630

Hi Team,

 

Our customer are evaluating LM3630A

However, “flicker” occurs at the following conditions.

 

 [Conditions]

-Linear Mapping Mode

-ILED = 10.25mA (2strings * 4 serial)

-Dimming PWM frequency =76.1719kHz

-Dimming PWM level (High is 1.8V / Low is 0V)

-Dimming PWM Duty = 4%

-Register 50h Bits [1:0] =”00”

-Register 05h, Bit 7 =”0”

-Register 05h, Bit 6 =”0”

 

I have two questions.

-----------------

[Q1]

I understand that recommended minimum dimming PWM duty cycle is 2%(typ) for all conditions.

If yes, could you please let us know the min and max value.


 

<Background>

Our customer would like to use “Dimming PWM duty is 4%”.

However, they have a concerns because this value has little margin for a recommendation value and “flicker” occurs.

-----------------

 

[Q2]

They changed Register 50h Bits [1:0] From “00” to “11”.

As a result, “flicker” was canceled.

However, we cannot understand a principle why a problem was settled.

I'd appreciate it if you could give me some advice about that.


-----------------

 

Regards,

Kanemaru

  • 0
    TI__Expert 3370 points

    HI,

    I don't think we have char data for the min Ton spec, following description was found on design document: 

    The minimum Ton pulse width required to produce a non-zero output is dependent upon the LM3630 settings.
    The default setting of the LM3630 requires a minimum of 0.78% duty cycle for the output to be turned on.
    Because the lower bound feature is enabled, a value of 0.78% (equivalent brightness code 2) up to 2.35%
    (equivalent brightness code 6) will all produce an output equivalent to brightness code 6.
    At 30kHz PWM input frequency, the minimum pulse width required to turn on the LEDs is 0.78% X 33uS = 260ns.
    Because of the hysteresis on the PWM input, this pulse width may not be sufficient to turn on the LEDs. It is
    recommended that a minimum pulse width of 2% be used. 2% X 33uS = 660ns at 30kHz input frequency.

    the filter strength 11 makes the PWM sampler output be averaged more, less sensitive to the duty cycle change.

  • 0 in reply to Sheng Jin
    Guru 21045 points

    Hi Sheng-san,

     

    Thank you for your prompt reply.

     

    Ton of our customer’s conditions is 525ns(4% * (1/76.1719kHz)) so this value is lower than 660ns (recommended value).

    Therefore, I understand that they have to rise Ton.

    Is my understanding correct?

     

    And, according to your comment, “less sensitive to the duty cycle change”.

    So, I understand that if dimming PWM duty has the Jitter, the recommended value of Register 50h Bits [1:0] is "11".

    Is my understanding correct?

     

    Regards,

    Kanemaru

  • 0 in reply to Hide
    TI__Expert 3370 points

    Yes, you are correct on both comments/understanding.

  • 0 in reply to Sheng Jin
    Guru 21045 points

    Hi Sheng-san,

    Thank you for your response.

    I understand. Thank you very much.

    Regards,

    Kanemaru