AM5726: AM572X EVK warm reset assertion and PMIC BOOT1

RATHEESH V S

Part Number: AM5726
Other Parts Discussed in Thread: TPS659037

According to the Silicon Errata (i862) for the AM5728 states that the porz SoC power-on-reset is the only 100% reliable reset type.but default condition for PMIC BOOT1 =0,it explains that

Single PORz release at startup,
no PORz during warm reset.

It means no porz release at Warm reset condition right?If warm Reset circuit works properly we need to ensure PMIC BOOT1=1,right

over 8 years ago

0 Cvetolin Shulev-XID over 8 years ago

TI__Guru 65405 points

Moving to Sitara E2E forum section.

BR
Tsvetolin Shulev

0 Biser Gatchev-XID over 8 years ago in reply to Cvetolin Shulev-XID

TI__Guru**** 393215 points

This can be best answered on the PMIC forum.

0 Karl Wallinger over 8 years ago

TI__Genius 16410 points

Hi Ratheesh,

You are correct, if BOOT1=0, then there will be no RESET_OUT toggling during warm reset. You can reference section 7 of the TPS659037 User's guide to see the warm reset sequences. Both diagrams show behavior with BOOT1=0 (in black) and BOOT1=1 (in green).

Regards,
Karl

0 RATHEESH V S over 8 years ago in reply to Cvetolin Shulev-XID

Prodigy 120 points

Dont clear, please clarrify

0 Karl Wallinger over 8 years ago in reply to RATHEESH V S

TI__Genius 16410 points

Hi Ratheesh,

I apologize for the confusion.

If BOOT1=0, then warm reset will have no PORz pulse. This means that RESET_OUT (connected to PORz) will remain high during warm reset.

If BOOT1=1, then warm reset will have a PORz pulse. This means that RESET_OUT goes high->low->high during warm reset.

To use the PMIC to workaround i862, you should set BOOT1=1.

Regards,
Karl

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AM5726: AM572X EVK warm reset assertion and PMIC BOOT1