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TPS63020: Schematic Verification

Gluonn R&I
Prodigy 235 points
Part Number: TPS63020

Hello there!

I'm designing a backup power system with boost converter that'll supply 3.3/5V from LiPo Battery. I'm using TPS63020 as BuckBoost Converter and TPS22910 as a switch. Here's what I'd like this device to do.

1. When USB is connected, TPS22910 will stop working. So, 5V will either be bought down to 3V3 or will be outputted according to Jumper (J1) selection.

2. When USB is disconnected, TPS22910 will turn on. So, LiPo Voltage will enter 63020. Output of regulator is dependent on Jumper(J1) selection.

I drew the schematic and need your help in verifying the same. Specifically, the following points:

1. In my design, user can select the output to be either 3V3 or 5V depending on jumper(J1) setting, Setting J1 to left will set the output to be 3V3 while setting it to right sets the output to 5V. I calculated resistances using R1 = R2(2Vout - 1) formula(Vref = 0.5V) as mentioned in DS. Can I change the output by selecting FB resistors through jumper?

2. I'd like user to have full control over converter. So, am exposing PS/SYNC and EN pins. Did I draw both connections correctly? Are PullDown on PS/SYNC pin(10k) and Pullup resistor(10K) on EN pin fine?

3. Did I connect PGOOD pin correctly?

Other than these three, is everything in schema looking good? Please let me know.

Teja

  • 0
    TI__Expert 8420 points

    I would recommend to use more capacitance at the the output, it looks like there is not 30uF effective output capacitance in the current circuit.
    Adding a 22uF capacitor in parallel would be better than increasing the size of the 47uF capacitor, as the ESL increases with the size and could be reflected on the output voltage. 

    1. The resistive divider looks fine, but I would not use values higher than 1 Mohm, What is your load profile? Do you want to change the output during operation?

    2. I don't see any issue with the 10kohm resistors. PS/Sync should not be left floating, what do you want to connect on this pin? How are you controlling the EN pin? 

    3. PGOOD looks fine for me

    What is the end application? Do you have a system level block diagram?

    The layout is a more critical part of the design, I could help you reviewing it also.

  • 0 in reply to Sabrina
    Prodigy 235 points

    , thanks for the response.

    As recommended, I've added 22uF Cap in parallel with 47uF Cap. Here's the updated schematic for you:

    Mitochondria_V1R1_Schematic.pdf

    1. The resistor combination I've designed will enable me to obtain the desired output voltages(Either 3V3 and 5V) will just 3 resistors instead of 4. To minimise BOM Count, I used these values. If you believe values beyond 1MOhms will crease an issue, I can add one extra resistor. Please let me know if it's absolutely required. The load profile will vary from user to user. We're looking at constant current draw will be anywhere between 100mA to 1000mA

    2. I'm trying to design a system similar to this. The end user has the flexibility to enable/disable Powersaving mode or disable the regulator altogether by shorting them with 1 or 0. That's why these pins have been exposed out on J2.

    3. Great!

    As mentioned earlier, I'm trying to mimick this.We're also looking at same consumer base.

    If everything is good in this Schematic, I'll start working on Layout. Thank you so much,  for offering help. I really appreciate it.

    Teja Chintlapati