hello
what kind of short issue do you observe? you can measure the impedance between others pin and GND to check which pin is short.
could you also share your layout of this boost converter?

Hello Jesper,

Did you look at the video's I posted here? I think that would answer your first question.

I don't mind sharing the layout, but I have read some of the replies you have given others in regards to their layout and you seem really focused on layout and have not provided any really helpful feedback as to why you think their layout is bad. So when you give me feedback on mine, please make sure and give me real details; I don't have patients for unhelpful support techs. If you're not up to it, then please pass this on to someone else in TI that will work with me.

sorry, the network in office is not good enough to watch the video.
the damage of the device, especially SW short to GND, is normally caused by the bad layout. the most critical component in boost converter is the output capacitor, which should be placed closed to the IC and route with strong and direct wire. otherwise, large SW voltage could damage the device. the layout you share is also not good. although i can's be sure if the layout is the root cause for your case.
for detail, please refer to this application note "www.ti.com/.../slva773.pdf".

by the way, the C2 in the schematic seem to be a tantalum or aluminum capacitor. but in the layout, it look like ceramic capacitor from the package size. could you share the part number of the cap?

Jesper,

Okay, I looked over the document you attached for layout and mine does not come close to that. I will start again and rebuild this board to those layout specifications. But I really want to make sure I do not end up with the same issue if I do match that layout.

C2 Part number is : F980J107MMAAXE DigiKey Par number is: 478-9836-1-ND

The video showed a working unit, with an input voltage of 4.1V (could go down to 1.2V) and an output of 5V. When I ground the EN line the system would stop working and a short in the IC would seem to happen. Something about when I GND EN line seems to cause the IC to break.

hello
here are some problem i currently found in schematic
1. the thermal pad of the TPS61090 seem not connect the PGND from the schematic and layout. it should be connected to PGND
2. the F980J107MMAAXE has 10ohm ESR, which will cause very large voltage ripple (datasheet page 15). i would suggest a capacitor with 100m ohm level
3. the Q1 seem to be placed in wrong direction.
4. the NT1 seem to be useless, you can remove it.

for the PCB layout, please following the application note i suggested and layout pattern in datasheet page 19.

for the observation in current board, it is not possible that the TPS61090 can switch at VIN=1.2V, the UVLO of this device is 1.6V:
1. please help to measure the impedance between each other pins and GND pin. so we can know which pin is damaged.

Hello Jasper,

Very helpful, thank you for the details.  

I update the C2 to TR3C107K010C0100.  

NT1 is the net tie for the two grounds, per the datasheet it said to keep this close to the input power.

Here is the updated schematic,

3021.LiPo_BAT_SPLY_V1C.pdf

Here is the updated layout:

For the schematic

the Ground of LBI and FB resistors are all signal ground, they should connect to signal GND firstly, then to PGND through single node. you can refer the Figure 14 in datasheet page 13 to understand my meaning. 

For the PCB layout

1. i would suggest change the C1 to a 0805 package ceramic capacitor, and placed as following figure. the SW can route under the capacitor.

2.  the Polygon Connect Rule change to "direct connect" in stead of "relief connect"

3. the signal GND should connect to the PGND between  the input capacitor and the output capacitor C2

Figure 14 shows FB divider on power GND and the LBI on PGND.  Updated based on this figure.

I updated the Grounds to match what it says in the datasheet: "Both grounds must be connected on the PCB at only one point close to the GND pin."

The C1 move won't work.  I added this snap shot so you can see the nets and know how things are.  

What does the pink area stand for?

what about move the C1 here, and place 4 vias closed to the PGND node of the C1, although not good as the former one, it should be also OK.

Pink is a keepout area so that I don't get ground pour under that inductor.

Okay here are the updates with C1 move:

One more place can be improved:
in the schematic, connect the pin 2 (NC) to PGND.
then in the PCB, the PGND of the C1 can be connected to the thermal pad on the top side. this will further reduce the parasitic inductance between the IC and the ceramic capacitor.

Okay great, I'll do that. Thank you for the work you have done with us on this!