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UCD3138064A: question related to update window size

jinsik park
Prodigy 110 points
Part Number: UCD3138064A

Hi TI guys,

I have a question about  updated window size.

PWM0 - LLC main PWM, PWM1 - LLC SR PWM

My test code is using PWM0 carrier is delayed 100 cycle with comparison to PWM1 because of driver delay.

( Dpwm0Regs.DPWMPHASETRIG.bit.PHASE_TRIGGER = 100; )

Recently, I have changed sample rate from PWM0 frequency to fixed rate frequency.

Previous version, PWM 0 deadtime = 250ns , PWM1 deadtime = 350ns. there is no problem.

After changing, PWM1 deadtime is changed to 1.1 ns... because of pwm1 pulse extension phenomenon. .. maby be addressed in datashet as update window size.

( phase delay (400ns) + window size (132ns) ) * 2 = 1064ns .. ... ? is this right? ..

pulse extension phenomenon is reproduced when hard dynamic condition. I have also checked this phenomenon is reproduced when pwm1 deadtime is from 350ns to 700ns.

064 -> 064a, update window size is change from 72ns to 132ns. I can agree about this fact. I don't know why I should consider phase delay part in this configuration.

Anybody tell me why? ...

  • 0
    TI__Genius 17090 points
    I'm not completely sure I understand the question, but I can explain the timing of the delay.

    1. The phase delay is on the output of the master DPWM. So DPWM0 sends a start pulse to DPWM1 100 cycles after the end of the DPWM0 period.

    2. When DPWM1 gets the start pulse, it starts its period. This starts the DPWM1 update window.

    If you are in normal mode, there are some good tricks to use for avoiding the update window issue. Unfortunately, in other modes, there are not.
  • 0 in reply to Ian Bower
    Prodigy 110 points

    My question is....

    Used scheme : phase delay 400ns, LLC PWM (multi mode + resonant mode), 1Mhz fixed samplerate, PWM0 270ns deadtime, PWM1 350 ~ 700ns

    I want to get hint why my system has PWM1 pulse extension in above case (especially in multi mode). ( pwm 1 pulse extension means that pwm1 gate turn off timing is delayed to next cycle. )

    I have solved above problem. PWM1 deadtime is changed to 1.1us. It's too large deadtime.. So, I want to know exact reason.

  • 0 in reply to jinsik park
    TI__Genius 17090 points
    If I understand your situation correctly, you should just need a dead time big enough to avoid the update window. You shouldn't need anything longer than that.

    I'm a little bit confused because you say that PWM 0 is delayed by 100, but you are writing to the DPWM0 phasetrigger. The phase trigger is on the output of the master DPWM going to the slave that needs to be delayed.

    What is the configuration of the DPWMs as far as master and slave, and which pin is getting pulse extension?
  • 0 in reply to Ian Bower
    Prodigy 110 points
    Sorry, I confused which signal is delayed.
    pwm configuration is as below.

    PWM 0 : master,
    Dpwm0Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN =0;
    LoopMuxRegs.DPWMMUX.bit.DPWM0_SYNC_SEL = 0;
    Dpwm0Regs.DPWMPHASETRIG.bit.PHASE_TRIGGER = 100;
    PWM 1: slave,
    Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1;
    LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0;

    If I use ~500ns deeadtime in PWM1, pulse extension is observed in PWM 1A channel.

    I have checked that stable EV1 position for PWM1 is ~400ns + 132ns.
    I want to know reason of above configuration.

    Thank you for kind reply.
  • 0 in reply to jinsik park
    TI__Genius 17090 points

    You haven't really given us enough information to understand the issue. 

    If you could give us the whole setup program for the DPWM as well as the limits on the filter which is driving it, that would be helpful.

    There's nothing obvious from what you've told us so far. 

    It would also be helpful if you could establish a sequence of filter outputs that would cause the problem.

    You can control the filter output by writing to the output clamp low and clamp high.  If you write the same value to both, that will be the output.

    It's best to do that on the open loop board, rather than the actual power supply, obviously.

    Normally it has to be a sequence, because the edge has to move in or out of the update window.

    You need to leave the EVENT_UP_SEL bits set to a 1 like the default.

    Note than another possible cause of pulse extension could be too much system noise getting into the UCD via the power supply or other pins. 

    Does this pulse extension only occur at very high currents? 

  • 0 in reply to Ian Bower
    TI__Genius 17090 points
    I've talked with the designer, and we've analyzed it further. If you are going to use the fixed sampling rate for the filter, you really need to have the two DPWMs synchronized with no delay. What is happening with your phase delay, is that the first DPWM is getting a period and starting, and then the filter runs before the second DPWM starts its next period. So the second DPWM is getting a different period. This means that the sync pulse from the first DPWM comes to the second DPWM before or after the end of its period. Both of these things can cause pulse extension of one DPWM pin or another. Probably by putting your large dead time in there, you are moving the start of the 1A pulse outside the maximum size of the change in the period.

    You either need to do your dead time some other way, without a phase delay, or you need to return to sampling synchronously with the DPWM period. Even if you do that, make sure that your sampling time isn't close to the beginning of the period, so it won't happen before the second DPWM has started.