TPS65094: Unexpected UVLO behavior

Hi Antony,

Do they clear the UVLO bit in OFFONSRC prior to step 3? UVLO bit will be set every time the PMIC powers up from UVLO, including the first power on. 

Are they measuring VSYS on the VSYS pin (pin 55) of the PMIC? This is where UVLO is detected and would give most accurate representation of what the PMIC is seeing.

Can they also monitor the THERMTRIPB signal? If there is a falling edge on it then PMIC will initiate emergency shutdown. 

HI Kevin,

Please check two waveform plots as described and let us know your comments.

1st waveform: PMICEN and SLP_S4 were turned off by EC after issue happened.

• THER is THERMTRIPB (CH1)
• EN is PMICEN(CH2)
• S4 is SLP_S4(CH3)
• ODL is RSMRSTB(CH4)

2nd waveofrm: VSYS level change in this plot is observed from their charger IC behavior,.  But noise is a little big.

• "LDO" means LDOA1. (CH3)
• CH1 is VSYS.
• CH2 is RSMRSTB

Thanks!

Antony

Hi Antony,

Thank you for the scope shots, they are helpful; as well as providing schematic via email.

Were they able to clear the UVLO bit in OFFONSRC before running the testing and seeing if it was reset? This will help confirm that we need to focus on UVLO or THERMTRIPB.

Additionally, I am still concerned about potential glitching on either UVLO or THERMTRIPB that we cannot see on 20 ms / division scale. Can you retake scope shots at smaller division (say ~50 us / div, triggering on RSMRSTB falling edge) and check the voltage on VSYS pin (either directly on PMIC pin or on C336) and THERMTRIPB pin (ideally directly on PMIC pin, though pin4 of U41 may be okay if it is near the PMIC). That will allow us to see much quicker glitches if they are present.

HI Kevin,

Thanks for comments.  Unfortunately they accidentally damage the PMIC chip on the board that they can duplicate the issue now.  They need to search for another board which can duplicate this issue for further measurements.

Please firstly check the waveform plot as below taken previously for VSYS(CH1) and RSMRSTB(CH4).   One question here is, if the PMIC is turned off due to TERMTRIPB, what will be shown on OFFONSRC register (considered it was cleared correctly previously)?  Is there any other possibility causing UVLO bit to be '1' in OFFONSRC register other than "VSYS drop below UVLO voltage"?

Antony

Hi Antony,

Thank you for the scope shot, it doesn't show anything suspicious but I think the larger microsecond range plot may have more dipping in the VSYS pin of C336.

There are no indicator bits for a THERMTRIPB related shutdown. So if they clear the UVLO and after the reset there is no OFFONSRC bits set, it would suggest a THERMTRIPB event.

UVLO bit is set when PMIC is in UVLO and then voltage on PMIC VSYS pin crosses 5.6V rising.

Hi,

Customer found another failed board and captured the waveform as below when the issue happen.  What is your comment?  What can we do to clarify if this issue is related to THERMTRIPB or anything else?  I'll try to clear ONOFFSRC register before duplicating the issue.  Please let us know what else we can do.

What do you think we can do to clarify why LDO5 (pin56) and LDO3 (pin 54) are so ugly here since VSYS looks ok?

Thanks!

Antony

Hi Antony,

Thank you for the additional investigation and scope shots. In particularly, it looks like LDO3P3 is power faulting which would cause the emergency shutdown. THERMTRIPB is pulled up to one of the bucks so the start of it's decay seems to match closely with the point that LDO3P3 drops below 3V, approximately the 92% powergood threshold. 

After some investigation from my side, an LDO3P3 power fault results in the UVLO bit being set. With LDO3P3 shutdown, the digital is completely disabled and when LDO3P3 reboots it is sensed as a return from UVLO. 

I think our next priority should be working on identifying why LDO3P3 appears to be struggling. My first suspicion is that there are soldering issues since this is only observed on a couple of boards. Let's take this discussion to email so that I can view the full schematic / layout as well.