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BQ24168: BQ24168 appears to be holding SDA line low

Kyler Connelly
Prodigy 10 points
Part Number: BQ24168

In my design on occasion the I2C bus becomes unusable because something is holding the SDA line low.

I have narrowed it down to the BQ24168. If I power cycle just this chip the problem goes away. I do not have the CD pin wired for the MCU to control, it is connected directly to ground.

Has anyone else seen this and have any idea what is causing it?

Thanks.

  • 0
    TI__Guru**** 167236 points

    Hi Kyler,

    We are not aware any issues with the I2C functionality of the bq24168.  If you cut the SDA line to the bq24168, running the charger in standalone mode, do you still have the problem?  What are the sequence of I2C writes to the bq24168 just prior to the SDA going low?

  • 0 in reply to Jeff F
    Prodigy 40 points
    Hi Jeff, et al.,

    We seem to be experiencing this same issue (bq24168 holding SDA low). We don't have visibility into what sequence of I2C writes occurred prior to SDA going low (as this issue resulted in the s/w attempting to release the SDA line (via SCL cycling), which wrote all over our log file content via the circular buffer).

    What are the most likely possible causes of bq24168 holding SDA low? E.g, Is there a sequence of I2C writes that may result in this behavior?

    It would be great if you could help at least to reproduce this error (e.g., by sending a specific sequence of I2C writes) since SDA was released by bq24168 when we disconnected the battery; but this is not an acceptable solution for us and we'd like to explore our other options.

    Thanks for your help,
    Paul
  • 0 in reply to user5040560
    TI__Guru**** 167236 points

    Paul,

    We are not aware of and did not design such a feature.  When the original post occurred, I attempted to recreate but could not.  What was VIN when this occurred? What is your pull up voltage for SCL and SDA?  What frequency are you running?

  • 0 in reply to Jeff F
    Prodigy 40 points
    Hi Jeff,

    Thanks for your quick response!

    VIN=5V.
    Pull-up voltage for SDA and SCL=3V.
    freq=90kHz.

    I noticed a few anomalies, which might help with this diagnosis:
    #1 I measured a rise time on SCL=1.34us and rise time on SDA=1.6us (exceeding the protocol spec). The pull-ups are 2.55kOhms. There are 3 slaves on this bus. Its a small board and I've calculated trace capacitance of ~20pF, 19pF from an I2C buffer, and 8pF from one of the slaves. I couldn't find a cap spec for bq24168. Do you have this? I'm also still trying to determine the cap on the remaining slave.
    #2 I see "blips" on SDA sometimes preceding ACK and sometimes following ACK (depending on which slave is responding). However, I haven't seen SDA change while SCL is high (and I haven't been able to recreate SDA hanging up). It looks like the blips are from the master releasing SDA to facilitate ACKs and the slave either pulls SDA low for ACK either a little late or it releases SDA a little soon. Is this common or "smoke"?
    #3 In order to facilitate routing traces on the board, pads under 3 of the PGND balls were omitted from the layout (as well as a pad under one of the BAT balls). I haven't seen any evidence of excessive noise on SDA or SCL. What kind of adverse affects might this have caused (and how could the effect be tested/verified)?

    Thanks again for your help,
    Paul
  • 0 in reply to user5040560
    TI__Guru**** 167236 points

    Regarding 1, pin capacitance is typically no more than 10pF.

    Regarding 2, per my digital designer "The spikes on the SDA line during the ACK phase are common in I2C. His hypothesis on the different timing of Master and Slave driving SDA during the ACK are correct."

    Regarding 3, missing PGND pads are not good for a variety of reasons, including thermal and EMI.  We are checking to see if one of the PGND pins are actually DGND for the digital.  If so, then that could be causing a problem.  Which of the PGND pads are missing?

    .

  • 0 in reply to Jeff F
    Prodigy 40 points

    Hi Jeff,

    Here are the locations of the missing pads for the WCSP (YFF) package:

    PGND: D6, D7, E1

    BAT: G4

    Thanks again,

    Paul

  • 0 in reply to user5040560
    TI__Guru**** 167236 points

    Paul,

    None of those are digital GND so we don't see a direct relationship between I2C issues and those pins floating.  Does this only happen when you current is flowing? 

  • 0 in reply to Jeff F
    TI__Guru**** 167236 points

    Paul,

    My digital designer just had a thought. When the IC ground not solid, it is possible when charging that ground bounce could generate a false clock pulse that causes the IC to pull SDA low. Is there a way to capture any SCL and SDA on the scope just before this happens? Does it happen after a write to start/stop charging?