Some clarification on the WAKE_M and RESET_M fields of the mask register. If these bits are asserted, does that mean that the associated function of the MR pin is disabled? In other words, if you set the WAKE_M bit then asserting MR will not take you out of ship mode? Also, can you clarify the HIgh-Z mode, paragraph 9.3.2? In high impedance mode, are the switcher and LDO actually regulating (off the battery)? the first part states
"During Hi-Z mode
the SYS output is powered by BAT, the MR input is active, and the LSCTRL input is active. All other circuits are
in a low power or sleep state.The LS/LDO output can be enabled in Hi-Z mode with the LSCTRL input. If the
LS/LDO output has been enabled through I2C prior to entering Hi-Z mode, it will stay enabled".
This implies that the SYS output and LDO are running off the battery. BUt then it says:
The CD pin is
used to put the device in a high-impedance mode when battery is present and VIN < VUVLO. Drive CD high to
enable the device and enter active battery operation when VIN is not valid.
What is "active battery operation" exactly? Thanks for the clarification.