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UCC21520: UCC21520 DT pin Can Floating

Wen Yung
Expert 1220 points
Part Number: UCC21520

Hi Sir,


May I know UCC21520 DT pin can floating? since currently we direct replace ADuM4223 occur output no PWM issues.

check input PWM is good. why?

  • 0
    TI__Intellectual 2910 points

    Wen Yung,

    Thank you for your interest in the UCC21520 isolated driver. I have contacted the applications engineer for this device to ask for his input. In the meantime, I can help you start with the debug.

    Regarding the DT pin: yes, it can be left floating. Leaving DT open sets the dead time to <15 ns, so this should not be an issue in most cases.

    What are your VDDA and VDDB values? Please note that for the UCC21520ADW these have an undervoltage lockout at 5V, and for the UCC21520DW the UVLO at 8V. The UVLO VDD_ON threshold must be satisfied at the device start-up time to keep the output from falling in the lockout state, during which the output is held low regardless of the state of the input pin. More details can be found in the Electrical Characteristics table (Section 6.9) and Section 8.3.1 in the device datasheet. 

    Regards,

    - Daniel

  • 0 in reply to Daniel Ruiz
    TI__Intellectual 2061 points
    Hello Daniel, Thanks a lot for your help.

    Hello Yung, As Daniel pointed out. DT pin can be float. and Floating DT will set the DT around 8ns.

    If your input PWM is in phase with each other, then the output will be low, please refer to the Figure 33. Case E, both output will be low when INA and INB are high. if you still have issues, could you please help to share your input waveform?

    Thanks a lot.

    Wei
  • 0 in reply to Wei Zhang
    Expert 1220 points
    Hi Daniel & Wei,

    Thanks a lot !
    Is good feedback to me, currently issue is High/Low side MOSFET shoot-through.
    I'll check dead time and update for you.

    Wen
  • 0 in reply to Wen Yung
    TI__Intellectual 2061 points
    Hello Wen,

    No problem at all.

    Btw, Here I paste some information from the datasheet for a kind reminder:

    Programmable dead time function.
    Tying DT to VCCI allows the outputs to overlap. Leaving DT open sets the dead time to <15
    ns. Placing a 500-Ω to 500-kΩ resistor (RDT) between DT and GND adjusts dead time
    according to: DT (in ns) = 10 x RDT (in kΩ). It is recommended to parallel a ceramic
    capacitor, 2.2 nF or above, with RDT to achieve better noise immunity

    Wei