TPS62260: TPS62260 Low Amplitude Output Oscillation

Could you post waveforms of what you are seeing (Vin, Vout, SW)? Did you install a feedforward cap?

Are the real system loads on the board and being powered or just these resistors?

The TPS62230 family is a newer device which offers smaller size, fewer components, and better stability with larger output caps.

Unfortunately the TI web-site is playing up at the moment and isn't giving me an option to upload any files so here is an initial reply to some of your queries :

a) the real system loads are not present, the only load is an 18R resistor. Have also tested with precision constant-current load (Agilent 39956) over a range from 10mA to 600mA with essentially no change to the output ripple.

b) there is a 22 pF capacitor across the upper resistor of the resistive divider in the feedback path.

c) the input is a steady +5V with ripple < 100mV pk-pk at the switching frequency

d) the SW shows a steady squarw-wave, 0V to 5V, period 430 nSec, High:Low ratio about 1:2

I'll try again later to load the waveforms & the schematic.

Robert Phillips

Hi Chris,

These are the waveforms

a) Input - scope DC-coupled 500mV

b) Input - scope AC-coupled 200mV

c) Output - scope DC-coupled 500mV

d) Output - scope AC-coupled 50mV

e) SW - scope DC-coupled 1V

f) Schematic

Robert Phillips

Thanks for the waveforms. Can you show Vout and SW on the same waveform at 20 usec/div?

Is the input filter installed? Can you test without it?

Do you have the part number used for the input and output caps? Did you use the same one for all caps on all 4 circuits?

Hi Chris,

Here are some more waveforms

1) OP  + SW at 20 uSec/div

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I thought the SW waveform above wouldn't reveal much, so have done a couple more as below to hopefully show the SW waveform more clearly.

2) Scope triggered on/near highest point of ripple with timebase at 100 nSec/div to show individual cycle of SW

    Yellow is OP  (looks flat because of very fast timebase)
    Blue is SW

3) Similar to 2), but scope tirggered at/near lowest point on output ripple.
    Yellow is OP  (looks flat becaase of very fast timebase)
    Blue is SW
    White - almost invisible behind Blue. This is a saved copy of the SW waveform from 2) - and shows that there is almost no
                 difference so SW waveform is almost the same at the highest and lowest excursions of the output ripple.

BTW. The ripple waveforms are obtained via a co-ax cable with screen bonded to PSU earth-plane and centre to OP
           The Sw waveforms are via a X10 scope probe with farly short earthing lead PSU earth-plane.

4) Re Caps
    I have asked for full part number etc bu the same cap was used on all four PSUS for input and output. These caps generic spec is
    10uF, 6.3V, X5R, 20%, 0603.

5) The 5V input filter is installed and it feeds all four PSU inputs.  It would be difficult to remove it but if this is really necessary I'm prepared to have a go.

6) FYI - There is actually a fifth TPS62260 fed from the same source generating -1V and this also is working fine with OP ripple < 10mV.

Robert Phillips

Yes, this is strange. It should be working, as it does for the other rails.

Normally, I would suspect an assembly issue. But you said that you checked a second board with the same results. I would try reflowing the IC and/or replacing the components around the bad ICs with fresh, known ones. Sometimes the wrong component is installed (on all PCBs in a lot).

It would be interesting to see if the behavior changes when some/all of the other rails are turned off. Based on your schematic, this would require cutting traces on the PCB to separate EN from Vin.

Hi Chris,

Unfortunately it would be very difficult to remove power from the other circuits as the power-plane in question is buried. A pcb assembly issue is possible, but then you wouldn't expect it to affect exactly the same devices on a second board.

Maybe I'll get another board built up with just this circuit populated and see what happens.

Somewhat related, I now understand that these devices have a fairly restrictive upper limit on the maximum load capacitance they can cope with. Is this correct, if so what is the maximum and what is/are the consequences if this is substantially exceeded? (in this application I would expect that load currents will be fairly steady apart from the switch-on surge of course.

You mentioned a newer family, TPS62230 which can handle larger load capacitances but I couldn't find any actual figures for this - do you know what the maximum values are?
(If these queries should be in a separate posting please tell me.)

Yes, it is important to consider the total output capacitance present on the bus and at the load, as the IC sees all of this. All TPS62xxx devices use internal compensation, so the output filter must be selected to match the internal compensation for stability.

Per the D/S, the TPS62260 uses voltage mode control which gives a narrow range of output filter for stability (section 9.2.2.2). This app note shows the measured stability range for a similar voltage mode control device: www.ti.com/.../slva441.pdf

Contrast this with the TPS62097, which uses DCS-Control (as used in the TPS62230: www.ti.com/.../slva710.pdf The output filter stability range is much wider.

The app note explains more about DCS-Control: www.ti.com/.../slyt531.pdf

Back on your original issue, you could try swapping the passives on a working voltage with one of the ones that shows higher ripple. This would show if the behavior follows the IC or its passives. If I understand your circuit correctly, you have the exact same schematic (except for 1 FB resistor) and layout used for 5 devices.

As well, you can post a working and not working PCB layout here (or send it to me in a private 'conversation') to have a second set of eyes look it over.

Hi Chris,

1) Re Large External Capacitors
   SLVA441 shows that the TPS6206x devices can be operated with up to 100uF total load capacitance provided that the inductor is correctly sized. Do you know if this has been tested on the TPS62260?

2) Re PCB Layout.
  Happy to show you this. I guess I'd need to convert each layer that carries PSU-related tracks to pdf or similar but not sure how to send these you you?

No, there is not a similar document for the TPS62260 family. I sent that one just to show the difference between the stability of the control topologies.

If you click on my name, you should find an option to have a 'conversation'. This is a private communication where you can share your layout. pdfs work fine.

Hi Chris,
Now talked to my pcb designer, he says if you prefer we can give you the pcb design in an ASCII format which many pcb packages eg Altium can read in. Alternatively we can stick with individual pdfs for each layer if you prefer. Your choice.
Robert

pdfs is fine. I can read Cadence files and Altium as well.

I've just sent you the pcb files via a private conversation session. Please let me know if you get them OK

Robert Phillips

Hi Chris,

As stated before, the current design isn't fully populated at this stage so the TPS62260s are only driving temporary external resistive loads. However, when the design is populated, there will be some large capacitive loads around 120 uF which is a long way outside the recommended maximum for this device so I thought I'd see what would actually happen if a capacitance of this size was attached. At very least, I was expecting it to radically alter the closed loop dynamics so that the output ripple would change significantly in frequency and, probably, amplitude.

To my surprise, the extra capacitance made no difference at all - the output ripple remained almost completely un-altered - see below - white trace is with 100uF tant, blue trace without. This seems very odd to me and maybe suggests that the output ripple is coming from some other source but there is nothing on the board other than the other three PSUs.

Does this suggest anything to you?

Robert

I can look at the files later today. Regarding the above, a better test would be to add the capacitance onto a voltage which is working 'normally'.

But 100uF of tantalum is different than 100uF of ceramic due to the ESR which adds a zero (and helps stabilize the loop).

The layouts look generally ok. But the GND plane didn't repour. Can you send a screenshot of what the actual GND copper looks like on the top layer?

It looks like you should be able to cut the trace to the EN pins (with a knife) to turn certain ICs off. This and swapping the high side FB resistor (to change the Vout on 2 ICs) could be tried.

Re Effect of 100 uF

I've now tried adding 5 x 22 uF x 10V x Y5V (all I could find at short notice) across the misbehaving PSU and, as with the 100 uF tant there is still no significant change in the output ripple. This which does not make any sense to me in view of comments in data-sheet about importance of value of total output capacitance.

- since these caps are  Y5V I did make a measurement to check that DC bias wasn't altering effective capacitance significantly.- drop was < 10%.

I've also put the same ceramic cap combo across a ripple-free PSU and again, no change - gives correct DC OP and ripple is < 10mV pk-pk with and without this cap.

My pcb designer is looking into your comments/query re pcb design.

Robert

Hi Chris,

Below is a screen-shot showing the copper pour(s). (Hope you can read it - only shows up in this post as a strange symbol)

Re Effect of 100 uF capacitors - have to admit I have no idea where to go with this so any suggestions, however unlikely, would be appreciated. Does TI offer a simulation tool suitable for SMPS like this?

Robert

Layer 1 flodded.doc

Thanks. It looks like the GND plane poured fully.

But I don't see GND vias near some of the rails. So, the GND has to travel across the board to get to some of the ICs. You might try applying 5V directly to the input cap of a bad rail and seeing if the behavior is different.

We have the models on the product page here: www.ti.com/.../toolssoftware

While it may appear stable on one unit, you may not get 'enough' phase margin when you measure the loop with a bode plot.

In fact there are a number of vias in the ground & power distribution planes near the ics and components making up these power supplies but these are invisible in the copper pour images.

Robert Phillips

I've now tried swapping the TPS62260 chips between a good circuit (no OP ripple) and a bad one (shows OP ripple). The result is that the bad one has become good and the good one is showing some ripple but not very large amplitude.

Seems to me this points to something to do with the chips themselves. Is it possible there is a batch problem?
Not sure where to go from here, this is the first change I've found which has actually had any clear effect - any suggestions?

For interest, I've also tried putting the 22uF x 5 caps onto the outputs of all the circuits and in all them them it does not seem to cause any noticeable change in the output other than to somewhat reduce the amplitude of any output ripple. This seems to contradict statements in the data-sheet about output capacitance values. Any comments would be appreciated.

Can you post waveforms of the ripple before and after?

Did you already try swapping the passives on good/bad circuits? How about replacing some passives with fresh ones?

I tried to address the output cap in my post yesterday--even though it may look ok on one unit, when you run the bode plot you may not get 'enough' phase margin (usually >30 degrees).

Here's the "before" waveform (ignore the blue trace, that's from the SW pin)

and here is "after" on the same scope settings

Can you post the other 2 waveforms? Initially good IC ripple and the same IC on the other PCB with its bad ripple?

Not quite sure what you are asking for but below is the ripple on the PSU output where the device from the "bad" circuit ended up. It is lower than was presnet when this chip was in it's original position, but is quite definitely present at more or less the same frequency as before.

I did not save the original "good" waveform but it was essentially flat with only the expected switching noise/ripple.

To further check this, I'm intending to take my other board, which has ripple on two of the four outputs and swap both pairs of chips. This will take a few days to happen, but I'll post all the results - before and after for all four.

Thinking about possible solutions, it might help to mitigate the effects of this cross-coupling if we were to substantially reduce the impedences in the feedback network by a factor of 10 or maybe even 100. Would this have any negative consequences?

Thanks for sharing your solution. I was just about to ask if you lowered the FB divider impedance to come to your solution.

Yes, this is perfectly ok per this app note, from the product page: www.ti.com/.../slyt469.pdf Be sure and increase the Cff by an equal amount.