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UCC28950: UCC28950 : what is the duration time from VDD applied to OUTx fixed to low ?

Naokazu Kinjoh
Intellectual 2740 points
Part Number: UCC28950

Hi team,
What is the duration time from VDD applied untill OUTx are fixed to low?
We presume those pins are high impedance for a certain period (eg, before VREF starts), is this assumption correct?
This is needed for designing.

  • 0
    TI__Expert 3200 points
    Hi Naokazu, I have forward this to our AE expert to help answer your question.
  • 0 in reply to Brian Johnson96
    TI__Mastermind 25570 points

    Hello Kinjoh-san

    OUTx will remain below 200mV at all times after VDD is applied until such time as the controller starts to generate correct pulses at the OUTx pins.

    I took the screen shot below this morning. You can see a small peak on OUTA to 180mV - OUTA increases with VCC until it reaches this point - this peak was absent when I reduced the dv/dt at VCC as you can see in the second image below.

    Yel: VCC

    Red: OUTA

    Blu: VREF

     VCC set to 12V, current limited source set to 2.0A. VCC applied through a switch to maximise the dv/dt. OUTA starts cleanly.

    OUTA was open circuit for this test.

     Peak OUTA voltage is 180mV

    OUTx events not correlated to VREF.

    Yel: VCC

    Red: OUTA

     VCC set to 12V, current limited source set to 130mA. OUTA starts cleanly.

    OUTA was open circuit for this test.

    I hope that this answers your question, please let me know if you need any  more information.
    Regards

    Colin