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LM5050-1: LM5050-1 OUT pin

Vivek Kumar45
Prodigy 20 points
Part Number: LM5050-1


Hi,

With reference to the statement below and the LM5050-1 datasheet, my understanding is that the "OUT" pin is just for protection means by sensing the voltage on the drain pin. If I donot want to use this pin and leave it no connect, my understanding is that gate voltage will be clamped to max 12V above the source/ IN pin to turn ON the fet. Is my understanding correct or am I missing something.

In forward operation, the gate of the MOSFET is charged until it reaches the clamping voltage of the 12-V GATE to IN pin Zener diode internal to the LM5050-1

  • 0
    TI__Expert 5940 points

    The 'OUT' pin must be connected in order for the LM5050-1 to function.  It is used to:

    1. Detect body diode conduction, which enables the 30uA gate current to turn on the FET. 

    2. Vds regulation (27mv) during normal FET on conditition

    3. Reverse current detection when a short occurs on the input so that the FET can be turned off rapidly.

    Brian

  • 0 in reply to Brian Daugherty
    Prodigy 20 points
    Thank you ! With reference to below app note: I understand that the input and output caps ensure stable VGS against noise on input or output pins . If my understanding is correct, can I use a 22uF ceramic capacitor on the output instead of a electrolytic cap as described in the LM5050-1 EVM app note? input cap would be 1uF. Voltage applied at VIN will be 20V max, Max continuous load of 40A in our application.

    www.ti.com/.../slva684.pdf
  • 0 in reply to Vivek Kumar45
    TI__Expert 5940 points
    Vivek,

    The EVM has a 22uF Electrolytic Cout with 1uF MLCC Cin. An MLCC is fine on the output. The Vgs stability app note SLVA684 refers to a case where Vin has very high audio noise (sine wave) on the input which results in Vout > Vin by at least the -28mv (nominal) Vsd reverse current detect where the gate is set to turn off, in that case inadvertently. This due to the lower dv/dt on the output vs the input when Cin < Cout and in the presence of a large Vin perterbation. To alleviate this, Cin was increased to 10x Cout which slowed Vin dv/dt to < Vout dv/dt and prevented the unintentional reverse current detect and kept Vgate untouched. The major reason for a difference in dv/dt between input and output side is that Vsd at light load is regulated to 22mv so the FET has 'higher' impedance across it vs just the Rdson of the FET and hence there is some decoupling between Vin and Vout caps by this impedance. So if you have input perturbations that cause Vgate to drop, you would need to do similar to the paper and increase Cin to higher value than Cout. This isn't always needed in designs, only special applications as noted. The other thing that helps is if load current is higher such that the gate is not in regulation mode and the FET is fully enhanced. This would be when (I-load * Rdson) > 22mv, but maintain this less than 100mv per the DS apps section recommendations.

    Brian