Hello Eric, is their more details about this expression?? for example reverse polarity will create -X voltage on the gate without the D6,Q3 & R2
Also Can you help in identify the effect of failure(short & open) for the following components ?

Q1, Q2,Q3,D4,D5,D1, only one component failure at one time

For (D3,D2) both at one time

0 Brian Daugherty over 8 years ago in reply to Abraham Choucair

TI__Expert 5940 points

Abraham,

See attached matrix of the external component faults you requested. These are our belief what would happen. Recommendation is that you duplicate this with your actual board/system to verify completely as this may be part of a Safety check. Note I attached a DS typo correction I noticed when going through, outlined in an attachement.

D6, Q3, and R2 provide fast protection against Q2 vgs voltage violation during reverse polarity. Vgate can be gnd or higher when Vin polarity is reversed, which would result in Vgs of Q2 far exceeding its typical rating of +/- 20v. Q3 is quickly turned on when its B-E is forward biased in a reverse polarity case and Vgs is pulled to 0v.

I want to also point out that the circuit in figure 39 has not been fully tested by TI for all operational scenarios (both forward and reverse polarity) and recommend you do so with your 1st prototype to your system specific needs.

Brian

Fig 39 component faults.pdf D4_D5 Typo in DS.pdf

0 Abraham Choucair over 8 years ago in reply to Brian Daugherty

Intellectual 530 points

Brain & Eric
Thanks for your support. This is fantastic information

0 Abraham Choucair over 8 years ago in reply to Brian Daugherty

Intellectual 530 points

Hello Brian,

If Vout is shorted to the ground . What are the actions that this IC takes for protection

0 Brian Daugherty over 8 years ago in reply to Abraham Choucair

TI__Expert 5940 points

Abraham,

Overcurrent protection is described in section 8.1.5 of the DS. It is a very basic level protection intended applications with higher circuit impedances that limit current rise. When the output current rises above the set threshold (uses Rdson of the FETs), the timer will activate and timeout, resulting in a fast pull down on the gate.

Brian

0 Abraham Choucair over 8 years ago in reply to Brian Daugherty

Intellectual 530 points

Hi Brain,
How about Reverse battery condition. What is the condition inside the LM5060 ? is the gate pulled to ground? or pulled high ???

Power management

Power management forum

LM5060-Q1: LM5060-Q1