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TPS54327: Output capacitance

Hirotaka Matsumoto
Guru 27585 points
Part Number: TPS54327

Hi all

Would you mind if we ask TPS54327?

<Question1>
The value of output capacitance is 22uF upto 68uF on the datasheet.
How much is the maximum value? Upto 200uF??

And in case of Cout=200uF, should we care followings?
-Phase margine for stability
-Soft start delay
-Pre bias start

<Question2>
In relation to <Question1>, for example, there is 10uF or 22uF ceramic cap in the subsequent stage circuit.
There are three subsequent stage circuits,  10uFx3=30uF.
In this case, does it(ceramic cap in the subsequent stage circuit) include total amount?
Usually, We guess that the total amount(output cap value) includes the subsequent stage circuit.
In this case, when our customer uses Aluminum cap(large ESR) at the subsequent stage circuit, transient responsiveness will decrease, right?
And we guess that it depends on distance(impedance) with the subsequent stage circuit.

Kind regards,

Hirotaka Matsumoto

  • 0
    Guru 27585 points

    Hi team

    We think your team is so busy, however could you give us the reply?

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 18510 points

    Hi Hirotaka Matsumoto-san,

    Please wait a moment, my teammate is looking into it, will reply to you ASAP.

    BR,
    Yuchang

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 18510 points
    Hi Hirotaka Matsumoto-san,
    Let me make some explaination
    For question 1, Basically, The LC value recommended in the table is for keeping LC double pole match with internal compensation to make sure loop stable. and the value should be verified by some test and simulation, so if use too large or too small Cout, that maybe cause loop unstability. if you use 200uf, and L make smaller, maybe can make LC pole in the range. but anyway, please also check Phase margin and SS ..as you said.
    For question 2, Yes, if two stage Cout circuits, total cap value should be considered, but I have no testing data i think ESR parameter should be a little affection for stable and for transient. Cout should be main element. and if the second stage is L and C, maybe this can cancel the second Capcitance stage.
    and whatever, follow recommendation value should be a safty application. others need do more verification.

    BR,
    Yuchang
  • 0 in reply to Yuchang Zhang
    TI__Guru**** 191445 points
    I have successfully used 200 - 220 uF output capacitance with these devices. I agree that you should verify your particular circuit by measuring the loop response on a prototype.
  • 0
    TI__Expert 4875 points

    Hi Hirotaka-san,

    I found issue before with output cap value more than 1000uF. In your application, if there is only 30uf second stage cap, it should be fine. 

    The main problem for putting large cap like 1000uf at output is stability and start up. The large LC will put the double pole at very low frequency and the phase drop quickly before crossover frequency. The phase boost of the internal zero from DCAP2 is not effective in this way. Also, putting large output cap will create a high inrush current and could trigger the overcurrent protection. Thus, cap more than 1000uf is not applicable in real application. 

    The best way is to double check the soft start behavior and bode plot on the real board.

    Best,

    Anthony

  • 0 in reply to Yuchang Zhang
    Genius 5355 points

    Hi Yuchang,

    1. Phase Margin & Soft Start Delay

    - How to check and what is deemed as correct value?

    2. How to check and confirm the correct value for soft start behaviour and bode plot on custom board?

    Thanks.

  • 0 in reply to ikon
    TI__Expert 4875 points
    Hi Ikon,

    1. Phase Margin & Soft Start Delay

    - How to check and what is deemed as correct value?

    For phase margin, connect a frequency response analyzer in your FB loop. Phase margin should be higher than 45deg. For the soft start, just monitor the Vout on scope and check whether Vout could built to nominal after soft start without any interruption and restart.

    2. How to check and confirm the correct value for soft start behaviour and bode plot on custom board?

    For soft start, follow on Q1. For bode plot, put an 50ohm( depending on your equipement) into your feedback loop( above the upper fb resistor). Use frequency response analyzer to inject and sweep an AC disturbance into the fb loop to check the system gain and phase.

    Best,
    Anthony