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BQ24295: Schematic Verification

Gluonn R&I
Prodigy 235 points
Part Number: BQ24295
Other Parts Discussed in Thread: TPS709, TLV707,

Hello there!

I'm building battery backup system(Power-bank Application) using 24295. I drew schematic and would like to clear some doubts. Can you give your inputs on the following?

Schematic:

1411.SCHEMATIC1 _ Mitochondria_V2.pdf

 

1. I want user to have control over charging enable and disable function. So, I've pulled-down the pin with 1k resistor and also have exposed the pin out so that user can pull it up, disabling the charging functionality. Is my connection fine?

2. I left the QON pin floating. Is it okay to leave it that way?

3. I calculated Kilim to be 475. I want to limit the charge current to 3A. Is the resistance of 150 Ohms okay on ILIM pin?(475/3 = 150)

4. Are pull-up resistors on SDA, SCL fine?

5. Are D+ and D- connections looking fine?

6. Is connection on TS pin okay if I use 103AT-2 thermistor?

7. Is resistance on STAT pin okay?

Is anything looking odd in the schematic for you? Do let me know.

Teja

  • 0
    TI__Expert 8230 points

    Hello Teja,

    Your schematic looks correct for the most part. Please see my comments below:

    • I recommend connecting the pull-up rail to either SYS or BAT, instead of the OTG output.
    • How is the user expected to pull the CE pin high to disable charge? Or are you referring to connecting a GPIO of the host to CE as well to pull it high in the event charge wants to be disable?
    • QON has an internal pull down, so this pin can be left floating if not used.
    • ILIM resistor is fine.
    • 10K pull-up resistors are fine for SDA, SCL. Please ensure the other devices on the I2C bus can handle the pull-up voltage, otherwise, level shifters will be necessary. 
    • D+/D- connections are fine.
    • 103AT-2 thermistor is the recommended type of thermistor to use. Change R14 to 31.23k.
    • The maximum sink current at STAT pin is 6mA. The size of the resistor on STAT will depend on the forward voltage of the orange LED you are using. For reference, on our EVM we use a green LED with a 2.21k resistor.

  • 0 in reply to Fernando Lopez
    Prodigy 235 points

    Hello Fernando!

    Thank you so much for your inputs.

    • Fig. 13(Page 20) in datasheet says that SYS voltage varies from 3.5V to 4.3V. While OTG Output will be 5V always. That's the reason I connected it there. Is there any reason why you recommended me connecting to SYS?
    • Aye. I'm exposing that pin outside. So, user can control it through GPIO.
    • Okay. Didn't change QON
    • Glad that ILIM resistor is fine
    • Next version will have 5 to 3V3 Level shifter. I really want to pull them up to fixed 3V3. Since that voltage is not available in the board, I have to pull them to 5V. Do you've any comment there? Should I connect them to SYS?
    • Changed R14 to 31.23k
    • The LED that I'm planning on using has a forward voltage of 1.9V while the Green LED used in EVM has FV of 2.1V. I changed my resistor to 2.4k

    Here's the updated schematic:

    8562.SCHEMATIC1 _ Mitochondria_V2.pdf

    Teja

  • 0 in reply to Gluonn R&I
    TI__Expert 8230 points

    Hello Teja,

    You can have the pull-up rail be on the OTG output. My line of thought was that if OTG gets disabled for some reason like over voltage or a short, we dont want to lose the entire I2C pull-up rail. If you plan on having a fixed 3.3V pull-up, you could use a very small and cost effective LDO on SYS  to provide 3.3V, like the TPS709, and save some development cost in the future.

  • 0 in reply to Fernando Lopez
    Prodigy 235 points

    Thanks for the reply. I really appreciate your valuable inputs.

    OTG being disable is a real possibility I didn't consider before. As recommended, I'll use some LDO and get 3.3V. I've had a look at TPS709 datasheet. Section 6.5 in page 6 says Vin should 1V greater than Vout. Section 8.2.1 in Page 15 says Vin should be from 5V to 20V. So, I think, we'll have to look at another part. Something like TLV707.

    Except for these, does schematic look good for you? Should I go ahead and start layout design? Is it fine to use 2 layer PCB for this design?

    Teja

  • 0 in reply to Gluonn R&I
    TI__Expert 8230 points

    Hello Teja,

    The TLV707 is a good alternative. Since the maximum dropout voltage at 3.3V is ~250mV, the MINSYS threshold on the bq24295 should be set to at least 3.6V, REG01[3:1] on the I2C registers. This will make the SYS pin voltage range to be 3.6V to the battery regulation voltage.

    For layout, we typically use 4 layer PCBs on our evaluation boards, but a 2 layer design is possible depending on the number of components needed to be routed. Section 11.2 of the datasheet includes an example layout with guidelines on component placement. Place the VBUS and PMID caps first as close as possible to the IC, followed by the BTST and REGN caps. Inductor and output caps for SYS and BAT following afterwards. High current paths, such as the PMID/SW loop should be as short as possible. Thermal vias underneath the device on the powerpad should be added in a 3x3 array. Thermal vias on across the board also help.

  • 0 in reply to Fernando Lopez
    Prodigy 235 points

    Thank you very much for your inputs. 

    I added TLV707 into my design. 

    I'll let my layout designer know about the inputs. Again, thanks for the help. I appreciate it very much.

    Teja