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UCD9090: RESET_N line concerns

Aaron Spaete
Expert 4577 points
Part Number: UCD9090


Team,

My customer has the following questions regarding the UCD9090.

There is a note in the UCD9090 datasheet:

 

I would like to further understand TI’s concerns with using the RESET_N line to power cycle the rails.

 

When I’ve used the PMBUS_CNTRL line to power cycle the rails, it worked nice, but I’ve got other design requirement’s where I want to reset the UCD9090 as well.

 

In the lab, using RESET_N to cycle the rails, I’ve noticed the following:

  • There is no sequencing off (The rails get disabled as soon as the UCD9090 goes into reset)

  • There is ~20ms delay after coming out of reset before the first rails sequences on.

 

If I can live with the two previously observed conditions, are there any other reasons why I cannot use the RESET_N line to power cycle the rails?

Regards,

Aaron

  • 0
    TI__Genius 9845 points

    Unlike analog devices, UCD90xxx’s RESET pin resets its digital core abruptly. All GPIO pins immediately enter high-impedance state, and all FPWM pins immediately enters drive-low state. There is no sequencing. Also, upon releasing the RESET pin, the device is subject to at least 20ms initialization time before it starts to function.

    The correct method to sequence off rails is to use CONTROL pin. A delay and dependency configuration of each rail is observed, and there is no initialization time delay at the following sequence on.

    Pulling reset pin when the device is logging faults will corrupt the log and cause INVALID_LOG status bit set and ALERT asserted. 

    The datasheet recommends pulling RESET pin to V33D with a local decoupling capacitor. This way, RESET pin voltage ramps up with V33D. Also, though unnecessary, users can opt to keep the RESET pin low by an external source until after the V33D supply has completed ramping up. But avoid pulling RESET pin low once the device is in operation. Glitch is not allowed on RESET pin.