UCC28600: UCC28600 questions

Nakai-san,

1. the pk-pk ripple on the VVD rail is not so important, there is no ripple spec that customer must meet. Usually a reasonably large VDD capacitor is required to keep the VDD pin > UV level during startup, and this usually results in very low VDD pk-pk ripple.

2. I will double check this with the author of the datasheet, and get an answer in the next 1-2 days.

3. You can use the datasheet design equations and rcommended design flow, or use the online Excel design calculator (www.ti.com/.../slvc104) to design your QR power stage. This will give a design that runs QR at Fmin ~ 40 kHz at max load and min input voltage (min point of low freq bulk cap ripple). As load decreases and/or line voltage increases, the freq of the QR controller will increase to maintain QR switching. This gives EMI benefits since the primary FET always turns on at the trough of the first DCM valley, so this reduces high freq CM EMI. The QR controller also maximise the operating dudty cycle which minimises the primary peak current, so this helps reduce DM EMI.


I will reply with more info for question #2 above.

Thansk,
Bernard

Hi Bernard,

Thank you very for the prompt reply.

I'm looking forward to receiving your answer for No.2.

Could I ask you a additional question about UCC28600.

How shoud we calculate R5 connected D1 in the EVM schematic on page4 of the following application?

Quasi-Resonant Flyback Converter Universal
Off-Line Input 65-W Evaluation ModuleUser's
www.tij.co.jp/.../sluu263c.pdf

Thank you again and best regards,
Kazuya Nakai.

Nakai-san,

The value of R5 is not critical, the value is usually chosen empirically by testing the circuit.

R5 is used to limit the peak-charging of the VDD rail due to the leakage inductance of the transformer. Usually it's value is small, between 1-ohm to maybe 47-ohm. Higher leakage inductance would need a slightly larger value for R5.

You would need to test your circuit to see what value works best for your own transformer.

Thanks,
Bernard

Hi Bernard,

Thank you for your support.
One of my customers asked us a few questions with their schematic.

Could you please help me because I can't answer their questions with poor technical knowleage about UCC28600?
If your answer is Yes, I'd like to discuss it with you directly. So could you tell me your e-mail address?

Thank you again and best regards.
Kazuya Nakai.

Hi Bernard,

Did you get any answer for Q2, 550mV question?

Thank you and best regards,
Kazuya Nakai.

Nakai-san,

Apologies for the delay in getting back to this.

I got some feedback from the author of the datasheet.

#2: The 550-mV term in the equations is actually an error. It should be the Vovp max value, i.e. -25 mV. The error in the datasheet will be corrected in the near future. Our apologies for any confusion caused by this.

#3: Regarding my comments above, the Fmin clamp is nominally 40 kHz. But in order to account for tolerances on this and external system (e.g. transformer mag inductance tolerance), it's best to use a design target of ~80 kHz for low line/max load, as outlined on page 25 of the datasheet.


If you want to share the customer schematic for review, you can email it to me at bernardkeogh@ti.com.


Thanks,
Bernard

Hi Bernard,
Thank you for the information.
I understood that 550mV was a error and the value must be -25mV, Vovp(Max).
By the way, do you think the online Excel design calculator (www.ti.com/.../slvc104) still can be used for peripheral parts parameter selection because the constant, 550mV is used in the calculator?

Thank you again and best regards,
Kazuya Nakai.

Nakai-san,

I will check if the design calculator has the same issue or not.


Thanks,
Bernard

The design calculator uses the correct value (25 mV) in its calculations:

ucc28600 design calc image.docx

Hello Lisa,

Thank you for your reply. I understood that the calculator can be used with no problem.

Thank you again and best regards,
Kazuya Nakai.

Hello Lisa,

Could you please give me your answer to my customer question below?

Q. My customer got all peripheral parts parameters by the ucc28600 design calc image.docx.
How much margin should they add to each parameter value?

Thank you and best regards,
Kazuya Nakai.

Hello Bernard,

Could you please give me your answer to my customer question below?
Q. We got all peripheral parts parameters by the ucc28600 design calc image.docx. How much margin should we add to each parameter value?
Thank you and best regards,
Kazuya Nakai.

The design calculator uses the typical parameters and thresholds from the electrical specifications on the data sheet.  It is recommended that the components used be as close as possible to the suggested component values calculated assuming 1% resistors, a primary inductance within 10% of the calculated result, and quality capacitors (X7R and C0G types). 

For a very conservative and robust design, you could re-calculate with the appropriate min or max values from the electrical characteristics table in the data sheet but the power stage components such as the input capacitor, the inductance value and turns ratios will not change. The biggest impact due to component tolerances will be to the OVP resistor divider, the power limit resistor, the current sense resistor, and the soft start capacitor. These components may need "tuning" based upon the min and max values.

Of course it would be easier to do the re-calculations if you could actually see the equations which I just noticed are not visible in the on-line available calculator. So here is a calculator that allows you to see the equations while I submit to get this updated on the website.

I hope this helps.

SLVC104I_viewable.xls