BQ24172: PWM unstable

Hi Aizat,

Can you please help to plot the SW, SRN, PVCC waveforms and provide the schematic? and have you try to used a real battery?

Hi Aizat,

Please also check the inductor, Caps, Rsense felllow '9.3.22 Inductor, Capacitor, and Sense Resistor Selection Guidelines' on the page 23of the datasheet.

Hello TI,

Below is the plot of SW, IL, SRN & PVCC:

Test condition:

• Vin = 12V
• Charge current = 1.5A
• Battery simulator
  • Vbat = 7V
  • Iload = 1.5A max
• Room temperature (25+/-2degC)

  

Below is the schematic of my charger circuit:

Nope, I didn't tried yet to charge a real battery. Nevertheless, the output gives good DC current (1.35A) and charging voltage (8.3V).

Looking forward on your feedback regarding my circuit issue.

Hello Allen,

Please refer to the schematic provided.

Tq.

Hi Aizat,

The schematic looks good. It may be Layout problems. How about the Location of BTST capacitor(CC6)? Please provide the layout and plot the BTST,SW waveforms.
BTW, please try to charge a real battery as well.

Hi Allen,

The wafevorm of BTST and SW are the same except the BTST = 5V+SW.

Attached is my PCB layout.

My PCB constraint:

1. The component placement must be on 1 layer (Top Layer) only.
2. The component placement must be positioned on the bottom of the Top Layer only with 54.00x9.00mm of area. Refer to the drawing.

Charger_module_layout_1A.pdf

I've already tried to charge with a real battery and the charging profile looks good. The CC current is at 1.4A, the charging voltage is at 8.3V and the termination charging is at 140mA.

I've tried to vary the value of CC18, RC4 & output cap but the PWM signal remains the same as original circuit.

What other tests I can perform in order to eliminate/minimize my instability PWM signal?

Thanks in advanced for your support.

Hi Aizat,

It looks a layout problem. You should follow below layout guidelines(Page 31 of the datasheet ), especially place inductor cloese IC, improve ground trace.

12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high-frequency current-path loop (see Figure 23) is important to prevent electrical and
magnetic field radiation and high-frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to switching MOSFET supply and ground connections and use
the shortest possible copper trace connection. These parts should be placed on the same layer of the PCB
instead of on different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals to keep the gate-drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 24 for Kelvin connection for
best current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use the copper-pour for analog
ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to
GND. Connect analog ground and power ground together using the thermal pad as the single ground
connection point. Or use a 0-Ω resistor to tie analog ground to power ground (thermal pad should tie to
analog ground in this case). A star connection under the thermal pad is highly recommended.
8. It is critical to solder the exposed thermal pad on the back side of the IC package to the PCB ground. Ensure
that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
9. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
10. Size and number of all vias must be enough for a given current path.
See the EVM design (SLUU396) for the recommended component placement with trace and via locations.