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TPS62150: switch node over & undershoot

Kalle Gronvik
Prodigy 140 points
Part Number: TPS62150

Hi,

the switch node voltage can exceed max ratings in certain conditions. I would like to know if these issues has to be taken care of?

I've attached two pics from two designs:  5 to 3.3V (on a simple breadboard), and 8 to 5V (from a PCBA with layout as shown in the data sheet).

1) The minimum switch node voltage rating of -0.3V is exceeded due to the inductor current through the internal pass diode when the synchronous rectifier is turned off. The first picture (5 to 3.3V design) indicates a min voltage of -0.76V.  it might be slightly better on a real PCBA.However, the second picture is from a PCBA, and there's still -0.7V undershoot. Is this acceptable?

2) Max ratings on switch node is Vin + 0.3V. As seen it can easily be exceeded due to the ringing at the node during discontinous mode. Do I need to add an RC damping to the switch node to reduce the peak voltage?

I always pay respect to the Max ratings, but I also would like to trust the designer of the device being aware of the actual behaviour of the design, so I'd like to think that the min voltage rating of the switch node actually is "better" than -0.3V. The max voltage rating I fear is more absolute?

BR

Picture 1: 5 to 3.3V on breadboard

Picture 2: 8 to 5.0V on PCBA

  • 0
    TI__Expert 5055 points
    Hi,

    please have a look in following paper: www.ti.com/.../slva494a.pdf
    It describes the topic in detail. The +-0.3V in the DS are DC ratings.

    Could you share the layout of your PCB design and a picture of the breadboard design?

    Best Regards,
    Michael
  • 0 in reply to Michael Helmlinger
    Prodigy 140 points

    Hi, thanks for the link. The undershoot seems OK then. However the pics in the appnote only shows continous mode so I would still be a bit concerned when the overshoot during discontinous mode reaches like 1V. For my present design though, I think it'll be OK.

    Pics of the breadboard & the old design layout attached :) The layout in pic 2 isn't exaclty as I would have done it, the current loop can be made smaller,  output feed to plane, and VOS, should be from the "outside" of the output cap, AIN and PIN aren't separated, and there's no separate decap for AIN.

    The layout for the new design show in pic 3. Note that PGND isn't connected to exposed pad directly at the device, only via the ground plane.

    BR/Kalle

    Breadboard

     

    8to5V layout (components on top side)

     

    New design (5to3.3V, components on bottom side)


  • 0 in reply to Kalle Gronvik
    TI__Expert 5055 points

    Hi Kalle,

    thanks for sharing.

    I'm actually surprised that your setup was working :) . As you know the layout is highly important for smps.

    The ringing during power save mode is not an issue. This is expected normal operation and is covered by the design. 

    The component placement looks OK in your layout. You may have a look in this paper: 

    It is a step by step layout guideline for this device family.