TINA/Spice/UCC2895: UCC2895

qi ye

Prodigy 70 points

Part Number: UCC2895
Other Parts Discussed in Thread: TINA-TI, , , UCC3895

Tool/software: TINA-TI or Spice Models

How design the external circuit of peak current control mode with UCC2895 in shifting phase full bridge?

over 8 years ago

0 Peter Fundaro over 8 years ago

TI__Prodigy 300 points

Hello Qi, I've contacted the appropriate applications engineer and he will get back to you.

0 qi ye over 8 years ago in reply to Peter Fundaro

Prodigy 70 points

Hi ! I'm using the UCC2895 and got some problems.When IC power on, I can't get 5V in 4(ref) footprint and sawtooth wave in 7(CT)footprint.It means the IC is not work and the Power is ok.

0 Oliver Pan91 over 8 years ago in reply to qi ye

TI__Intellectual 2230 points

Hi Qi,

Would you share your schematic to let me know how did you configurate the IC and what is the voltage at VDD pin? Please notice that VDD should great than UVLO thershold(11V) to get the IC work.

Thanks
Oliver

0 qi ye over 8 years ago in reply to Oliver Pan91

Prodigy 70 points

This is the schematic and it's peak current control.The voltage of VDD is12V.Please help me check it out.

Thank you!

0 qi ye over 8 years ago in reply to qi ye

Prodigy 70 points

Hi! The problem was solved.Can you give me some documents about UCC2895 in peak current control. I confused by downslope compensate.

Thank you!

0 Oliver Pan91 over 8 years ago in reply to qi ye

TI__Intellectual 2230 points

Hi Qi,

You can refer to the application note of UCC28950: www.ti.com/.../slua560c.pdf
And the article about loop compensation of current-mode control as below: www.how2power.com/.../H2PToday1004_design_TexasInstruments.pdf

Thanks
Oliver

0 qi ye over 8 years ago in reply to Oliver Pan91

Prodigy 70 points

Hi Oliver,
Firstly,Thank you for your help!I study some documents about UCC3895.There is a transistor between REF(4 footprint) and RAMP(3footprint),its purpose is to realize the downslope compensate in peak current control.Can I directly connect the CT(7 footprint) to the RAMP(3 footprint)? If it is ok, the capcitor between RAMP footprint and GND is useless,can I take if off?

0 Oliver Pan91 over 8 years ago in reply to qi ye

TI__Intellectual 2230 points

Hi Qi,

To minimize loading on the oscillator, it is best to buffer the timing capacitor(CT) waveform with a small transistor between REF and RAMP. The small capacitor between RAMP and GND works with a resistor as a filter to bypass the noise from current sense.

Thanks
Oliver

0 qi ye over 8 years ago in reply to Oliver Pan91

Prodigy 70 points

Hi Oliver!

I'm really appreciate for your help! I study the datasheet and user's guide again,and get some questions.

1. The output of the small transistor connect a resistor to the RAMP, how to design the value of this resistor?

2. Assume the VBE=0.7V, it means that only the voltage of sawtooth above the 0.7V, the RAMP footprint can get the voltage. This will result in the duty ratio jump in smaller duty cycle, is there any methods to solve this problems?

3.The ADS and CS footprint has a resistor respectively, how to confirm the value level?

4.This is my control schematic, please help me check it out.

Thank you!

0 Oliver Pan91 over 8 years ago in reply to qi ye

TI__Intellectual 2230 points

Hi Qi,

The calculation of slope compensation components is suggested on page 3-106 and 3-107 of U-111, the app-note describes the whole details better than I can. For the ADS configuration, please use equation 5&6 in the datasheet to determine the resistors divider. The resistor value should as large as possible to avoid sourcing too much current from CS but need to provide enough bias current(+-20µA) for this pin.

Thanks

Oliver

0 qi ye over 8 years ago in reply to Oliver Pan91

Prodigy 70 points

Hi Oliver,
Thank you for your help.The document is very useful,I will study in detail.
Thanks
Ye Qi

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TINA/Spice/UCC2895: UCC2895