Hello,
I have an LM5117 application where floating converters may be connected with outputs in series and have independent enable lines.
If I attempt to enable the converter via the UVLO pin (standby level to operating level) when there is current forward biasing the lower FET, the controller does not start, holding both the SS and Vcc pins low. This state is maintained as long as there is current present (possibly 0.5mV CSG +ve wrt CS). This is doing what I need, can TI confirm that this is intentional or, at least inherent in the design as it is not evident from the block diagram on p11 of the data sheet.
tks, JJW
