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TPS65381A-Q1: When does EnDRV pin clear

Bob Bacon
Genius 10815 points
Part Number: TPS65381A-Q1
Other Parts Discussed in Thread: RM48L952

Hi

For our project using the RM48L952 + TPS65381, we are trying to decide the best way to terminate a function when an error is detected. We have decided that any error in a peripheral or hardware associated with the product will cause the product to reach a safe state and halt. How we achieve this is unclear…but we can see that we can use the ESM to provide a FIQ, or a nError signal.
One will cause a watchdog failure, and the other is directly routed to the companion chip (TPS65381). 

 

We intend to use the Q&A watchdog and understand that both (if desired) can cause the Companion chip to “Go Safe” (EnDrv inactive). We understand that the Companion chip will place the processor in a reset state, but we are unclear if this is held until the power is removed or the processor is allowed to reboot.

 

Please can you clarify or point me in the direction where the information is.

Thanks
Bob Bacon

  • 0
    TI__Mastermind 20590 points

    Hi Bob,

     

    The best place to see a summary of all the conditions that will cause the ENDRV pin to go LOW, thus in most applications shutting off the safing path to the power outputs is figure 5-14. The ENDRV pin is under a combination of controls that the MCU and the TPS65381 have to control whether it is HIGH or not.

     

    As you will see first, no fault conditions should be detected in the TPS65381, the watchdog fail counter (WD_FAIL_CNT) has to be < 5 and the MCU must SET the ENABLE_DRV bit in order for the pin to be HIGH. If the TPS65381 detects watchdog "out of range" the ENDRV pin will go low once WD_FAIL_CNT is > 5, thus ENDRV goes LOW before the count reaches the level to go to RESET state which would cause the MCU to reset.  Any condition that causes the TPS65381 to go to SAFE state will also make ENDRV go low. 

     

    If the customer is using software traps to find system errors they have several choices on how to make ENDRV go low depending on their system needs:

    1. Clear ENABLE_DRV bit, ENDRV will go low. No impact to TPS65381 device state.

    2. Cause watchdog failures: send bad answers (Q&A mode, since you mentioned ESM they have to have the WD in Q&A mode).Once WD_FAIL_CNT > 4 ENDRV will go low, if they keep sending bad answers the TPS will transition to RESET state once WD_FAIL_CNT reaches 7 + 1 (next bad event after the count is at 7).

      1. If the bad answers are sent to cause RESET, the TPS device will transition to RESET state causing NRES to go low which will normally cause reset in the MCU.

      2. NRES will remain low for the reset extension time, programmed by the resistor on RSTEXT pin (figure 5-16 and figure 5-1 help explain this). In this case the VDDx power will not be removed, the TPS device will just transition to RESET (NRES low) then DIAGNOSTIC states. 

    3. Intentionally cause a failure on the ERROR/WDI signal going to MCU ESM, that will cause SAFE state and ENDRV will go low.

    1. Once in SAFE state what happens to the TPS device states depends on the DEV_ERR_CNT and how the customer has configured SAFE_TO[2:0], SAFE_LOCK_THR, PWD_THR, , and NO_SAFE_TO bits. Below is a revised state diagram that helps make the SAFE state paths more clear.

    2. The summary below will help them understand SAFE STATE TIME-OUT impact on SAFE state and the exit from SAFE state depending on the configuration programmed in the registers.

     Best Regards,

    Scott