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TPS3850: TPS3850 / tWDL and tWDU at SET0=0, SET1=1

S.Satoshi
Guru 21685 points
Part Number: TPS3850


Hi,

Now I'm calculating tWDL and tWDU at SET0 and SET1, then the tWDL(max) may be higher than tWDU(min) as attached. I think this means there is no valid window at considering WDI timing from MCU. Can you confirm it and give your comment?

Best Regards,

Satoshi / Japan Disty

  • 0
    TI__Genius 12630 points
    Satoshi,

    You are correct. In the configuration SET0 = 0 and SET1 = 1, there is possibility for the lower boundary and upper boundary to overlap. This is mentioned by Note 3 below table 6.6 on page 6 (( (3) If this watchdog ratio is used, then tWDL(max) can overlap tWDU(min). )). Because the lower boundary window is calculated as a ratio of the upper boundary, choosing SET0 = 0 and SET1 = 1 sets a 3/4 ratio meaning both boundaries are large compared to the Valid Window. For this case, I recommend using ceramic capacitors with COG dielectric material so the capacitor tolerance plays a smaller role in the window timing tolerance. Also, the probability of the upper window being at the min and the lower window being at the max is low but there is still the chance there is overlap.

    -Michael