Hello
Please help me.
When I designed the active clamp with the UCC2897A chip, I did not understand the equation 49 in the application file SLUA535.
Question 1: How to determine whether the core has been reset, or which parameters can indicate that the core has been reset.
Question 2:How should I design the primary inductance, leakage inductance and clamp capacitance to ensure the resonant period and core reset time.
Question 3:Assuming that the time required for the core reset is t, then t should be less than (1-Dmax)*Ts.
This is my understanding, if my understanding is wrong, please correct me.
Regards
Neil
