Can you speak to the EMI/RFI or transient immunity of the operation of this device?
Example: the datasheet gives the propagation delay from EN falling to GATE falling. One could naively interpret this as being proportional to the response time, and bandwidth, of the internal comparator and drive circuitry. Would this be a reasonable assumption?
Another way to put it: what's the shortest pulse width, and how far below the EN threshold must it be (as a function of pulse width), for the IC to respond? Surely it does not respond instantly, i.e., that V(EN) < V(EN_L) is absolute, and guaranteed to trigger for any instant of time.
The same question follows for the other functions: enable, current limit, fault, UVLO and so on.
Could there be any sensitivity issues, i.e., that noise (high frequency AC, or rapid switching transients, or high dV/dt) on any pins (particularly, the supply or current sense pins?) have an impact on the operation of the device?
An example of this kind of "undocumented" behavior includes most bipolar op-amps: RF at the input pins becomes rectified by internal structures, resulting in an erroneous input offset voltage, and detected RF; PSRR dropping to zero (or even less!) at frequencies beyond those plotted in the datasheet; etc. (While this exact mechanism is less of an issue for CMOS designs (I don't know if the part in question is CMOS, BiCMOS or what; your datasheets never give this information anymore), it is only a matter of degree.)
I don't have a specific application and example handy, these are simply questions that I ask of all devices I design with, and I expect your engineers will easily be able to answer.
Can you provide an estimate of how much transient or RF voltage (vs. frequency) can be tolerated without violating the specifications?
Thanks,
Tim
