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BQ76930: bq76930 equalization FETs damaged during short circuit tests

Sheldon Rubin
Intellectual 540 points
Part Number: BQ76930
Other Parts Discussed in Thread: TIDA-00449

We have a problem with balancing FETs getting damaged during the short circuit test. We're using CSD17484F4T FETs with a 33 ohm series resistor and a 5.6V zener from gate to source.

This does not happen every time and when it does it's usually (but not always) the FETs connected to BT1 and BT2. We're using a 7S4P battery with Panasonic NCR18650B cells.

Our design is similar to the one shown in TIDA-00449 for the bq76930 and balancing FETs. All of the filter caps are 220nF and the filter resistors are 1k0. I think everything is within the recommended ranges.

Short circuit current is set to 17.8A with a 100 microsecond delay.

Would putting a TVS across each FET be the most likely solution to this problem? If yes, what current rating would be recommended?

Thanks for your help!

Sheldon

  • 0
    TI__Guru 54715 points
    Hi Sheldon,
    It is hard to imagine why the FET would be damaged. The 3 things which come to mind with a broken FET would be exceeding Vgs which has the zener, Vds which is 30V for the CSD17484 or the FET power. The voltage limits of the CSD13381 used on the TIDA-00449 are lower so yours would be considered a stronger design. The FETs will turn on during short circuit since the cell voltages drop below the input filter voltage, the bottom FETs have the least to drop. You might want to probe your system to see what is happening during the short which could cause the damage. Check to be sure the zener is effective in those locations. One would not expect the cell's inductive response to be larger on the lower cells, but interconnect could push low cell voltages below VSS depending on where VSS is referenced.
    Your specific question on selecting a TVS for the FET, you would want to select a TVS with a working voltage above the normal cell voltage so that leakage would be small. The clamp voltage or at least breakdown should be below the FET Vds limit. Current into the TVS (and FET) will be limited by the balance resistor during clamp