LP8860-Q1: LP8860-Q1

Hi Yoav,

Unfortunately the only parameter that controls the threshold for input OVP is the OVP_LEVEL[1:0] register and as you mention this has a max of 22.5V. So best solution is masking the Vin OVP as you have already done.

Best Regards,

Salome

Dear Salome,

A few additional questions :
Is it possible to work with either 3.3V or 5V with the LP8860A-Q1 ?
What is the difference between the different LP8860A/B/C/D/E ?
Is it possible to receive the part pre-configured to the customer's requirement ?

Best regards,
Nir.

Hi Nir,

If you want to use VDD 3.3V, then charge pump would have to be enabled. Internally, VDD rail is used to drive the gate of switching FET. When VDD 5V, this provides enough voltage to drive the FET but VDD 3.3V will not for most applications, that is why in that case charge pump should be enabled to double the VDD voltage and provide enough voltage level to drive the FET. You can re-program the EEPROM of LP8860A to enable charge pump and allow 3.3V VDD.

There are several LP8860 versions which cover most applications, but the EEPROM can always be re-programmed to meet specific application conditions if needed. We cannot pre-configure devices but we can provide recommended EEPROM values for your application.

We have an application note that covers all version details for LP8860 "Selecting the Correct LP8860-Q1 EEPROM Version". You'll need to request access to LP8860-Q1 tools first. You can do so from LP8860-Q1 product page by clicking on Request Now:

If you have already done so, you should be able to access LP8860 files/tools by going to myTI -> My activity -> mySecure software, and find app note under Technical Documents.

Hope this helps,

Salome

Thanks for your respons and additional information, it help a lot..

i have additional question:
can you tell what would be the maximum voltage on the out1\out2\out3\out4?
In our design we will have FET transistor drain connected to this point (gate will be connected to control).
i'm worried about the transistor Vgs voltage too low for openning the FET drain-source path.

Thanks in advance..

Hi Yoav,

The maximum voltage on the output pins will be determined mainly by these three registers: DRV_HEADR[2:0], DRV_LED_COMP_HYST[1:0], and DRV_LED_FAULT_THR[1:0].

These registers will determine the level of the internal LOW, MID and HIGH comparators respectively which are then used to control the adaptive boost and determine whether short or open LED faults occur.

During normal operation the output pins will be mostly operating between the LOW and MID comparator level (DRV_HEADER[2:0] + DRV_LED_COMP_HYST[1:0]).You can calculate this level with your specific EEPROM settings but if we consider worst case scenario and set to max values, output pin voltage could be up to VSAT+1V+1V ~2.75V (typical saturation voltage is 500mV, but max up to 750mV). 

But if there is high Vf variation on the different strings or if an Open/Short condition occurs, the output pins will reach the HIGH comparator level before setting a FAULT. The DRV_LED_COMP_HYST[1:0] will determine this LED fault threshold and can be set to max 10.6V.

So back to your question, FET transistor would have to be able to operate with min gate voltage of DRV_LED_COMP_HYST[1:0] + Vgs voltage.

Best Regards,

Salome