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BQ76940: Timing bounds of the measurement schedules

johanf
Prodigy 110 points
Part Number: BQ76940

I am currently tracking down a bug which appears to be caused by an insufficient waiting period after TEMP_SEL changes. The BQ76940 datasheet contains the following note on page 25: "When switching between external and internal temperature monitoring, a 2-s latency may be incurred due to the natural scheduler update interval."
However the datasheet does not appear to specify any bounds for this parameter and so what is the recommeded minimum safe delay period which we should be using?

Judging by the timing bounds of the protection functions it may be as high as 3.5s. Though these are difficult to extrapolate from given the large variance between settings.

I would also be interested in any other effective strategies for minimizing the worst-case time between cell temperature measurements when sampling the die temperature since a twice the presumed 3.5s plus sampling jitter lands us uncomfortably close to the 10s alarm period specified for the product.

  • 0
    TI__Expert 6085 points

    the 2 seconds time stamp is by design of the Scheduler. For in-depth time stamp of the scheduler, please refer to the Scheduler document ( application report SLUA775-August 2016, " Embedded Scheduler in cell battery monitor of the bq769x0). The  document is downloadable from inside  bq76940 product folder.

    txs

    vish

  • 0 in reply to Vish Nadarajah
    Prodigy 110 points
    Thank you, I was unaware of that document.

    If I am interpreting the application note correctly then the TEMP_SEL write will take up to two 125ms communication periods to promulgate up to the top of the stack. Followed a the conversion within 2s. And then two additional 125ms periods for the results to reach the bottom of the stack. Multiplied by the oscillator tolerance.

    Judging from the block diagram each cell bank uses a 256 kHz oscillator for both OCD monitoring as well as the scheduler. And the former is specified at ±20%.

    So that yields a delay of 3s (= (2s + 125ms x 4) x 120%). Would that be a correct analysis?
  • 0 in reply to johanf
    TI__Expert 6085 points
    very close; since the GB includes the voltage and temp variations.....
  • 0 in reply to Vish Nadarajah
    Prodigy 110 points

    Thank you. That seems to have resolved my issue.