hi, all
I am trying to use TPS25940 in some design that uses 3F super-cap connected to its output and having some issues
Requirements for the device:
- Input voltage comes from power plug, 5V nominal;
- I want to have PGOOD signal indicating sufficient voltage level at output super-cap, this is around 4V. PGTH voltage divider is connected to output super-cap;
- I want to detect the disconnection of external power supply and to use this signal at MCU to backup some data. MCU is powered from the super-cap while this happens, it takes around 10 sec to complete it.
- I also want to have the same signal if input voltage goes out of range, to start backup;
The issue with TPS25940 is that once the internal MOSFETx2 switch is ON, it conducts both ways. When input voltage is disconnected, the output voltage from super cap passes to input and it appears that input voltage is still there. From the description I understand that automatic disconnection will work only if there is a sufficient backward current flow around 240mA from output to input. However, when this current is zero - MOSFET switches still ON all the time. Basically I am unable to detect the loss of input voltage!
I tried two extra options:
1) I probe the input behind an additional blocking diode (on the anode which is connected to power plug, cathode goes to IC). While this works to some extend there is power loss (current is 1A) and voltage drop of 0.3V which reduces the working range for my [expensive] super-cap. I also connect UVLO/OVP voltage divider before the diode. Second issue here is that once input voltage disappears, UVLO triggers #FLT signal which is OK, but next PGOOD signal also disappears because IC goes into shutdown. But I still have enough voltage on super caps. So PGOOD does not reflect real voltage anymore and the only way to have it is to use external comparator.
2) I use extra current sense IC to detect that input current goes to zero which means that there is no power coming in. This also works to some extend. However. I am unable to detect UVLO condition as input is powered from output. This fails when I gradually reduce input voltage to UVLO threshold and under it, but output super-cap voltage is higher (it has been charged earlier, when voltage was high).
Basically, only the current limit works for me with this IC and I need up to 10 extra components to do the job. This looks like a work-around rather than normal design.
Should I give up this chip and use something else?
