BQ24610: Layout Example

Hi Tateo,

Please refer to the page 32 of the datasheet(section 12.1). I also provide the giude below.
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high-frequency current-path loop (see Figure 23) is important to prevent electrical and
magnetic field radiation and high-frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to switching MOSFET supply and ground connections and use
the shortest possible copper trace connection. These parts should be placed on the same layer of the PCB
instead of on different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals to keep the gate-drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 24 for Kelvin connection for
best current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use the copper-pour for analog
ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to
GND. Connect analog ground and power ground together using the thermal pad as the single ground
connection point. Or use a 0-Ω resistor to tie analog ground to power ground (thermal pad should tie to
analog ground in this case). A star connection under the thermal pad is highly recommended.
8. It is critical to solder the exposed thermal pad on the back side of the IC package to the PCB ground. Ensure
that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
9. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
10. Size and number of all vias must be enough for a given current path.
See the EVM design (SLUU396) for the recommended component placement with trace and via locations.
For the QFN information, see SCBA017 and SLUA271.

Thank you for your reply. Let me confirm GND connection of EVM. They consider to refer to board layout of EVM.

- Where is the point that connecting analog GND and power GND of EVM?
  I think it is under the thermal Pad. Is it right?

- Which layer does it connect power GND to analog GND? I think it is only 2nd layer. Is it right?

- They would like to know that what type of the each solid GND either analog GND or power GND. I think that it is as follow:

    Top layer: Power GND and Analog GND *These GND are separated
    2nd layer: Power GND and Analog GND *Tehse GND are connected under the thermal Pad
    3rd layer: Power GND and Analog GND *These GND are separated
    Bottom GND: Only Power GND

  Is it right? Could you check the following comments?

Best Regards,
tateo

Hi Tateo,

You are right， upper half is PGNG and lower half is AGNG. They are connect under the thermal pad.

Alen Chen