TPS56121: Problems with the working of TPS56121

With EN/SS low, the device is disabled. Can you see why EN/SS is 0 V? Also can you post your schematic and PCB layout?

Hi John,

             Thank you very much for showing interest on this. I am attaching the schematic and the gerber files for your reference.

Regards

Varun h rTPS56121-1_schm.pdfGerber_TPS56121_final.zip

Hi,

At first, you need to check the Enable pin to make sure it's a high level.

In the schematic, it seems that the compensation is not correct. you need to choose the zero of the compensation near the LC pole.

Thank you!

Hi Vental,

Thanks for your feedback, as I have followed WebBench design straight away, not worried about compensation.
Can you please explain more about "choosing the zero of the compensation near the LC pole".

Regards
Varun h r

Hi:

1, I don't think the value of the out cap in your schematic is correct, in the WEBENCH, the output cap is 47uF*3. If you increase output cap, you need to adjust the parameter of the loop, such as the value of Ccomp3, CComp, Rcomp 

2, For the explanation about "choosing the zero of the compensation near the LC pole". As we know ,for a stable loop, we want the gain attenuate with -20dB/Dec and the phase margin is 45 degree when the gain is 0, but with the voltage mode control(TPS56121), the inductance and output cap will  bring two poles[1/(2*Pi*sqrt(LC))], the attenuate rate become -40dB/Dec what we don't want, so when we need to add the zero to resist the pole, that why choosing the zero of the compensation near the LC pole.

3, By the way, change the output capacitor and check the circuit, if it still couldn't work, please capture the waveform of the SW, VIN, VOUT, EN.

Thank you!

HI Vental Mao,

                       Thank you very much for your detailed explanation. Will follow your guidelines and let you know what happened. 

Regards

Varun h r

Hi Vental Mao,

We are working on the loop stability, one more bad thing is we are observing Power good signal (Pin 22, PGD) as a 0V on our board, but on EVM board its 5V. As per datasheet Power good signal low when

I can't see the image, would you mind to upload it again?
As for PGD, if the output is normal, the PG pin is high because of the high-pull resisitor RPGOOD.
For the Vfb, if the EVM work well, the Vfb must be 0.6V, maybe your EVM also didn't work well .
please capture the waveform of the SW, VIN, VOUT, EN when the power on
By the way , make sure the satisfied current of the inductor is big enough in your circuit.
Thank you