LM5023: Valley switching operation

Hi Mahendra,

Thanks for reaching us. LM5023 device does not have a “true” valley detection mechanism to detect the valley, instead it waits for a configurable “delay time” t_DLYQR after the demagnetisation of the X'FMR and senses the auxiliary voltage to fall below the 0.35V threshold before turning on the FET to “predict” the timing of the ringing to reaches the lowest value i.e. the valley. As the resonate frequency of the V_DS ringing is depending on the primary inductance and COSS of the FET, so we can predict the valleys easily and sets the corresponding delay time. 

This delay time is determined by the value of Cd capacitor and the values of R1 and R2, for more details please refer to Section 8.2.2.3 Valley Switching Equation 52 to 55 in the LM5023 datasheet. 

And back to you question, yes are right about switching at first valley will have less switching losses and that is most of the design tends to do.

One potential reason why PMP8865 switches at third valley could be to keep the switching frequency below 75kHz for high line condition in order to keep the second harmonic component away from the 150kHz EMI band. We are still verifying this with the designer of PMP8655 the reasons behind this and any potential harms for switching it at first valley.

Please note the PMP designs are often customised for targeting a specific application that requested by our customers. So it could be the special requirement for the application.  

I hope this will help, and please let us know if you have any further questions. 

Thank you.

Best Regards,

Wei-Hao