TPS7A6350-Q1: Watchdog Enable of TPS7A6350-Q1

Hi Masami,

The timer is initialized by the conditions listed in Table 2.  

The watchdog circuit is considered digital and is initialized at the time of the event that caused the initialization.  After the event causing initialization occurs, the first WD pulse must occur within 8 x twd.

Very Respectfully,

Ryan

Hi Ryan-san,

Thank you for your reply.
I understood about initialization condition of Timer.
However, the customer is investigating the cause of the circuit malfunction.
The most important thing to know is the time from the rising edge of the nWD_EN pin until the Watchdog fault no longer occurs.
I want to know if this time is less than 1 uS or about several uS or about several tens uS.

Thanks, Masami M.

Hi Masami-san,

Okay, I think I understand what you are looking for now.  You are looking for the time from the watchdog being disabled (nWD_EN going logic high) to the watchdog fault clearing.  This time should be less than 1.65us.

Very Respectfully,

Ryan

Hi, Ryan-san,

Thank you for your reply.
I answer it to the customer.

Thanks, Masami M.