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TPS7A8300: TPS7A8300

William Lorentz
Prodigy 30 points
Part Number: TPS7A8300
Other Parts Discussed in Thread: TPS7A47, TPS7A49, TINA-TI

Are there tables of stable ESR values for the TPS7A8300 and TPS7A4700?

  • 0
    TI__Guru 50060 points

    HI William,

    Do you mean for the Any-Out(TM) pins? If so these are shown in the following block diagrams:

    TPS7A83:

    and TPS7A47:

    Did this answer your questions?

    If not please let me know.

    Regards,

  • 0
    Prodigy 30 points
    Sorry.............no. I meant the acceptable range of ESR to maintain stability for the capacitor on the Out pin. It is referred to as ESR stability boundaries graph in AN-1482.
  • 0 in reply to William Lorentz
    TI__Guru 55940 points
    Hi William,

    In general LDOs, such as TPS7A8300 and TPS7A49, are now being designed with ceramic capacitors in mind. Each datasheet should state if there are specific ESR requirements (TPS7A49 states that ESR should be 200mΩ or less for stability); however, capacitor compensation and LDO stability will be application dependent (What transients are expected? How is the PCB laid out? etc).

    It is certainly worthwhile and recommended to build a prototype that allows a variety of capacitors to be tested. This testing should include worst case transients and look at the transient response of the LDO. EVMs are available to aid in testing.

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    Prodigy 30 points
    Thanks Ryan.....

    I understand that there are many factors that influence the regulator's performance. My ultimate goal was to attempt a stability analysis of the Regulator and associated components from a control systems / transfer function (loop gain, bw, poles & zeros) point of view (similar to TI's SLYT194).

    Can you provide any insight into whether or not enough information (error amplifier output impedance, series pass element capacitance etc.) is available to me for these specific regulators?

    Otherwise, my only option is to go with your original suggestion and perform some experiments using your EVM.

    Regards,

    Bill Lorentz
  • 0 in reply to William Lorentz
    TI__Guru 55940 points
    Hi Bill,

    We do not typically provide all of the information used in the journal calculation.

    In general, we want the effect of the output capacitor to be outside of the LDO bandwidth. The bandwidth of an LDO can be estimated by a PSRR curve. To estimate, you take the point where the PSRR curve begins to roll-off. If you extend this 20dB/decade decay to where the line would cross zero dB, that frequency is approximately the bandwidth for the LDO. For TPS7A8300 the bandwidth is ~500kHz.

    As such, we would conservatively want 1 / (2*pi*Resr*Cout) to be greater than 5MHz.

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    Prodigy 135 points
    Hi Ryan

    I was too into stability analysis of this LDO TPS7a8300 to study the effect under wide load variation(including -ve resistance load) ,can I get any average model (I wasn't able to get TINA TI model) so that I may hook it up with some controller(PID probably) to test the stability of loop .I am planning to design automatic voltage control (LDO will be in adjustable mode) by feeding voltage into Feedback pin through DAC and sensing output voltage.
    Regards
    Anmol
  • 0 in reply to Anmol Kapoor
    TI__Guru 55940 points

    Hi Anmol,

    We offer both TINA-TI and PSpice transient models under the Tools & software tab of the product folder.  Here is a direct link for your convenience:

    www.ti.com/.../toolssoftware

    Please note that another beneficial way to analyze stability across various conditions is to use a prototype board and subject the LDO to transients while monitoring the output.  We offer EVMs for TPS7A8300 in the same location as the models.

    Very Respectfully,

    Ryan