UCC28070: Could you tell me about UCC28070's design method.

Hi Matsumi-san,

①-1：How do you decide the optimum value of the peripheral parts of the Current detection ports (CSA, CSB)?

(Answer example 1: When VPKLMT = 3.3 V, average voltage of VCSA / VCSB is _ _ V and load current flows by _ _ A)

(Answer example 2: VPKLMT = 3.3 V, IOUTLIMIT = _ _ A, VCSA / VCSB can be decided by expression _ = _ _)

It need a lot of information to link CSA/CSB voltage to load current, please refer to the calculation in application-note of UCC28070.

①-2： Is it OK that is to feedback from VREF by "VPKLMT = 3.3V"?

(Because it is a specification that VPKLMT can change, this pin also does not know whether 3.3 V is optimal)

The programming range of the PKLMT voltage extends to upwards of 4 V to permit the full utilization of the 3-V average current sense signal range, however it should be noted that the linearity of the current amplifiers begin to compress above 3.6 V. So 3.3V is OK for PKLMT.

②In the application Diagram, the current sense is sensed with an AC signal using a transformer, but is it possible to design by detecting by using a shunt resistor "M1 / ​​M2 's above or below"?

A current-sense transformer (CT) is typically used in high-power applications to sense inductor current while avoiding significant losses in the sensing resistor. The UCC28070 use a single resistor(RSYNTH) programs the synthesizer down slope. This eliminates the need for the diode-leg CT in each phase, significantly reducing space, cost and complexity. If you want to use sensing resistor, place it in the switching leg to obtain the up-slope current and the down-slope current in the diode leg is obtain by the internal current synthesizer.

③Is the input signal to the system usable at 42 to 69 Hz (50/60 Hz ± 15%) at AC?

Yes.

④When disabling the operation of IC (UCC 28070), which terminal should be controlled?

The first way is pulling down VSENSE pin below 0.75V, almost all of the internal circuitry is disabled if VSENSE < 0.75V. When VSENSE is released and reaches 0.75V and VAO < 0.75V, the oscillator, multiplier, and current synthesizer are enabled and the SS circuitry begins to ramp up the voltage on the SS pin.

The second way is pulling the SS pin below 0.6V, immediately disables both GDA and GDB outputs without fully disabling the voltage loop and multiplier. when the external SS pull-down is released, normal PWM operation resumes if no other fault conditions are present. Please refer to page 26 in datasheet for more details.

Thanks

Oliver

Masumi,

①-1, the recommended maximum voltage of CSA/CSB pin is 3.6V refer to datasheet, for best control, you should select CSA/CSB as high as possible. The recommended maximum voltage of PKLMT pin is also 3.6V. normally, I_PKLMT=(120%~150%)*I_CSA, I_CSA represent peak current of full load, I_PKLMT represent cycle by cycle current limit threshold. So, you should select CSA/CSB based on PKLMT=3.6V and rate of I_PKLMT/I_CSA you defined.

Because peak current of full load is known, you can set voltage of CSA/CSB by I_CSA*R_SENSE/Turn_ratio of current transformer. To minimum size of current transformer and reduce power loss of R_SENSE, the Turn_ration should be high, suppose 100:1.

①-2： Is it OK that is to feedback from VREF by "VPKLMT = 3.3V"?

Of course. If you set VPKLMT=3.3V, you also low down CSA/CSB pin voltage, which affect ITHD/PF. You should balance them.

②There is no theoretical reason that prevents the UCC28070 from working with shunt resistance. But current sensing with shunt resistance has higher power loss and higher cost(should apply amplifier), it is not recommend to use shunt resistance.

Regards,

Yunsheng