LMR14030-Q1: SYNC input

Hi,

As RT pin is not ideally high impedance, it has impedance Rz as shown in below fig. As R30 is low enough, so the Vsync =Vcoup*Rz/[(R24+1/S*C26)||R26+Rz], adding R24 and C26 parallel with R26 low the impedance (R24+1/S*C26)||R26, which will result in lower voltage drop on (R24+1/S*C26)||R26. For R24, it's lower the better in theory, but will result in large coupling current, I think 4.02k is an trade-off value derived from experiment.

One more suggestion, it's better to choose a larger C26 (say 22pF or 33pF) if your SYNC clock I/O port is strong enough.

Thank you for your reply.

By the way, they evaluated sync operation by EVM and found SW jitter. This jitter is bigger than other IC. Is there any way to reduce SW jitter?

Best Regards,
tateo

What's your load of this condition? The SYNC function is not applicable at PFM mode. see page 14.

Thank you for your reply. The measurement condition is as followings.

Vin=12V, Vout=5V, Load current=2.5A

Best Regards,

tateo

Tateo, I also evaluated that on our EVM, it's about 15~20ns jitter. Just want to confirm someting with you.
1. What's the point you apply and measure the SYNC clock?
2. What's the load? Is the load constant 2.5A or is there any transient?
3. Is the VIN stable? Is there any transient.
4. Have you tried an function generator instead fo the MCU I/O port?

Thank you for your support. Could you share us your screenshot? How much is the resolution of your screenshot?

1. The point which be applied and be measured is J2.

2. The load is constant 2.5A.

3. VIN is stable. Stabilized DC power supplies to VIN.

4. Yes, they also tried an function generator. The result seems same.

Best Regards,

tateo

Tateo,

Below is the waveform tested at the same condition as yours in our lab. Full band width 250MHz, 2.5GS/s.

Did you test the waveform after the soft-start is completed?

Have eyou tested the jitter w/o SYNC clock?

If you already tried everything, and still could not find the root cause. Suggest apply a new EVM for testing.