TLV1117LV: failed devices

HI Sam,

Would you mind sharing a schematic? I am interesting in seeing how the super-cap and buck are used. Is the super-cap on the input or output of the LDO? Any scope plots you can share showing power up, power down along with the transitions to and from back-up power would help us to better understand what may be happening.

This is the first I have heard of this type of failure mode, so their may be some unforeseen stress on the device in the application.

Also, I would encourage you to contact your local sales support to submit the devices for failure analysis.

Regards,

Hello John,

I can show you a block diagram, but unfortunately I am not allowed to share any detailed schematics publically.

I have some measurements of the 5V rail:

Startup behavior:

2.3A load step:

normal shutdown:

last gasp (backup power shutdown):

Here is another capture of startup (both 5V and 15V rail):

HI Sam,

Thank you.

I do not see anything to be concerned about here. How about the VIN and VOUT startup/shutdown behavior of the TLV1117LV? Is there any chance either of these voltages are going negative or do you see VOUT being greater than VIN during shutdown? Just wondering if there is a pulse of reverse current going through the parasitic body diode of the LDO FET.

How much total capacitance do you have at VIN and VOUT of the LDO?

Regards,

Hi John,

Yes, I forgot to mention that is also one of the things we have considered.

I have some plots of the 3 voltages (green=15V,blue=5V,pink=3V3).

Startup:

Shutdown:

3V3 seems to follow 5V exactly, which rules out reverse current because otherwise there would be a diode drop difference between the two. Am I right about this?

Here is the behavior at backup power shutdown:

Again the 3V3 seems to follow 5V exactly, no diode drop.

We did some test before with a TLV1117LV without any load and a large output cap. We unplugged the device and expected there would be a reverse current from the cap discharging to the 5V rail, but the device seemed to have no issue with reverse current going to the 5V rail.

Hi Sam,

Thanks for the scope shots, they are very helpful. Looking at the zoomed in portion of the last scope shot it's possible that there is some reverse current events occurring but it's hard to tell. If you look closely you can see places where the pink trace is higher than the blue trace this could simply be due to the limited resolution since we are zooming in on a waveform that was sampled at a lower frequency. If you can it would be great to re-look at this portion of the waveform without using the zoom feature of the scope so that the time per division is much smaller and therefore the sampling frequency is increased for a cleaner image. 

If you can it would be great to re-look at this portion of the waveform without using the zoom feature of the scope so that the time per division is much smaller and therefore the sampling frequency is increased for a cleaner image. 

-Kyle

Hello Kyle,

Thanks for the tips.

I have some more scope plots that show the waveforms in greater detail.

Meanwhile I have also connected a short loop of wire at the input pin of the LDO to measure the current with a current probe.

I think we indeed have some reverse current spikes at shutdown.

Colors are: Yellow=current at input pin of the LDO,green=15V,blue=5V,pink=3V3

Following shot gives an overview of the shutdown.

Next shots show the highest spikes (about -200mA)

There's also some reverse current later in shutdown (about 100mA):

The datasheet mentions the following regarding reverse current:

The PMOS pass element in the TLV1117LV device has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited; if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended.

What does "extended reverse voltage operation" mean in this context? The reverse current peaks last for only a few 100µs.

Would you expect damage to the device at these kinds of currents? We have only had a few failures so far. Any idea what the failure mechanism is like? Does the LDO fail immediately if the reverse current is too high, or does it degrade and then fail? If the PMOS fails, we would expect the output to be basically 0V. In our case the voltage is about 1.5V under load which seems to indicate the PMOS is still able to conduct some current.

I just tried breadboarding a circuit in which I forcefully generate a reverse current through the LDO. Something like this:

I now measure reverse currents of over 1A for roughly 200µs, yet the device seems unaffected.

It seems very unlikely that such a large reverse current would ever occur in our product. 

Of course I only tested this on a single device and only a few times, but I'm a bit baffled that the device is not damaged by such a large current considering the 5% reverse current rule of thumb.

EDIT:

I did another test using a constant load of 1.5A at the input. No input voltage, 3V3 applied to the output. The device gets very hot, but continues operating fine once I reapply 5V at the input.

Hello Kyle,

Thanks for your reply.

I agree that we should avoid this situation in our circuit, possibly by placing an additional reverse diode across the input and output terminals.

However, the failure mode you are describing does not seem to match what we are seeing in our failed components. So even though it should be fixed, I am not sure it is the cause of the failures we've seen.

If I'm interpreting this correctly, reverse current would likely cause an open circuit in the main path. So essentially, no current would be able to flow from input to output (aside from any bias or leakage currents).

What we are seeing, are components where the LDO voltage drops to 1.5V (instead of 3.3V) under load and increases to about 4.4V with no load. Furthermore the diode seems to be intact (I measure 0.7V from output to input using diode tester). And this is pretty consistent across the failed components. So I don't see how an open circuit could cause this kind of behaviour. Or could this be part of the "degrading" you are describing?

I'm having a hard time trying to estimate how the circuit might behave under these conditions. If it just increases the drain-source resistance, I would not expect the voltage to increase to 4.4V without load. Or is the degrading more like a fundamental change in the I-V characteristic of the PMOS?

I've tried to reproduce the behaviour we are seeing through simulation, but have had no luck so far...

EDIT:

I did some measurements on a failed LDO. This graph shows the output voltage of the LDO versus the load current at various input voltages. 

There is no voltage regulation anymore and the LDO isn't able to handle any substantial current at all. Would it be possible to figure out what part of the LDO has broken based on this behaviour?

I don't know if the internal circuitry is at all similar to the conceptual diagram shown in the datasheet?

Hello Kyle,

OK thanks for clearing that up.

We are going to do some stress tests on 20 of those parts to see if we can reproduce the failures.

Kind regards,

Sammy