Other Parts Discussed in Thread: UCC28063
In my application the PFC will need to cleanly recover from interruptions as long as 200ms. Currently what happens is during the interruption the COMP pin winds up as expected due to feedback. Slowly initially due to the low bandwidth, then rapidly when the feedback crosses 5.8V and the fast 100uA source cuts in. When the mains comes back online the PFC now draws a huge inrush as the COMP is now clamped at the maximum. Also at 200ms it is too short to trigger any of the internal brown out behavior to the UCC28061 which require 440ms.
My plan was to reset the external slow start I had already fitted as the default slow start using the compensation network was way to severe. This external slow start was the RC (10k/22u) from VREF. For startup this works great but VREF is only switched when the IC comes out of UV or the PFC output voltage is extremely low.
So my plan was to the PWMCNTL output as this has the Phase Fail as part of its logic. I also needed an extra MOSFET for signal inversion. The problem is during the interruption the PWMCNTL does not seem change state even though the gates show the classic missing phase restart behaviour eg pulse every 200us. What I am suspicious of, is that a phase fail will not be signaled to PWMCNTL if both phase are non operational. If this is the case then my plan will not work. So some confirmation of this would be appreciated or some other comments on the validity of my idea.
Attached file shows some plots and circuit.
