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LP8758-B0: data transfer sequence

tateo yamashiro
Guru 10890 points
Part Number: LP8758-B0

Hi,

We got a question from customer about LP8758-B0.
Could you help us?

[Question]
They are evaluating LP8758-B0 by their board. When they set FPWM mode and 0.7Vout, the master send the below data.

               address      data
 step 1:     0x02          0x083a3a3a3a
 step 2:     0x0a          0x1100
 step 3:     0x1e          0x151515
 step 4:     0x03          0x3a
 step 5:     0x0a          0x14
 step 6:     0x02          0x8a

Regarding their data transfer sequnece, is there any possibility that the IC will be damaged or failing the data transfer?

Best Regards,
tateo

  • 0
    TI__Genius 9655 points
    Yamashiro-san,
    I assigned your request to the product specialist who will respond to you.
    Best regards,
    Frank
  • 0
    TI__Intellectual 810 points

    Hi Tateo,

    From the recorded data it looks like the customer performed the following:

    Step 1: Discharged resistors enabled, EN2 pin controls BUCK0+Enable roof/floor control+Discharge resistors+Forced PWM operation with forced multi-phase operation(Repeat)
    Step 2: Buck Voltage set to .67V
    Step 3: Masking for load current measurement ready interrupt INT_TOP, Interrupt not generated, Load current measurement ready.
    Step 4: BUCK0 switch current limit set to 5.0A(Default), voltage slew rate set to 10mV/us (Default)
    Step5: Buck Voltage set to .7V
    Step6: Buck0 regulator enabled, discharge resistor enabled when buck0 is disabled, forced to pwm operation with forced multi-phase operation

    Could you provide scope shots of the steps mentioned above? Can you also confirm that the above steps that I mentioned is what was intended by the Customer? Is the customer attempting to switch between two voltages , .67V and .7V using the Roof/floor funcitonality? If so I don't see where they set the BUCK0_Floor_Vout, defined in register 0x0B.


    -Raymundo Hernandez-Toscano

  • 0 in reply to Raymundo Hernandez-Toscano
    Guru 10890 points

    Hi, Thank you for your reply. They intend following.

    Step1: Disable Buck0, only EN_BUCK0 bit controls BUCK0, EN1 pin control, Enable/Disable control, Discharge resistor enabled, PFM ON, Phase shedding ON, Buck 0/1/2/3 ILIM=5.0A and 10mV/us slew rate
    Step2: Buck 0 Vout is 0.67V, BUCK0 Floor voltage is 0.5V
    Step3: I_LOAD_READY_MASK and TDIE WRN_MASK is 1, Buck0/1/2/3_ILIM_MASK is 1, BUCK0_PG_MASK is 1
    Step4: Buck0 ILIM=5A, 10mV slew rate
    Step5: Buck 0 Vout is 0.7V
    Step6: enable Buck0, only EN_BUCK0 bit controls BUCK0, EN1 pin control, Enable/Disable control, Discharge resistor enabled, Forced PFM ON, Phase shedding ON

    Could you check their data transfer sequence again?

    Best Regards,
    tateo

  • 0 in reply to tateo yamashiro
    TI__Genius 11020 points
    Hello,

    Step 3 write starting from address 0x1E has some error, since it is writing to reserved register bit. So I would change it to 0x051515. Other than that I don't see issues with the sequence. There are some duplicate writes, but it should not damage the device or cause problems. For example the step 4 is not needed, register 0x03 is already written with 0x3A data in the first step.

    Does customer have evaluation module? It would help with the debugging and figuring out the write sequence.

    Thanks.

    Best Regards,
    Tomi Koskela