• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 65 subscribers
  • Views 1749 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC2895: Asymmetric duty cycle at start up

Allen Wachter
Expert 6730 points
Part Number: UCC2895
Other Parts Discussed in Thread: UCC3895

Customer running into some start-up issue with UCC2895. An asymmetric duty cycle is observed during the start-up condition. He followed the instruction of SLUA275 to add a DC bias to Ramp Pin, but the problem is still there.

 

Also it mentioned that if UCC2895 operated at the Voltage-control mode, there’s no this problem. How does one configure the UCC2895 to voltage-control mode?

  • 0
    TI__Expert 3200 points
    Allen,

    An AE will respond to your question.
  • 0
    TI__Intellectual 2230 points
    Implementation of voltage mode control is by applying a fixed frequency sawtooth voltage to the RAMP pin, this signal can be generated from the a fraction of the oscillator timing capacitor (CT) waveform or other inputs with sync frequency of internal clock, simply remove the R2 in the Figure 2 of SLUA275 can realize voltage mode control.
  • 0 in reply to Brian Johnson96
    TI__Mastermind 25570 points

    Hi Allen

    The UCC3895 can be configured for voltage mode control by connecting the RAMP pin to the CT pin. The current sense signal is of course disconnected from RAMP but kept in place at the CS pin. To prevent transformer saturation you will then have to add a DC blocking capacitor in series with the transformer primary. The control law is different too in voltage mode control (VMC) as opposed to (peak current mode) PCM control so the compensation network would have to be redesigned. Also, when the system hits current limit - that is when the signal at the CS pin gets to 2V peak - the system reverts to PCM. This isn't a problem in itself - the controller is protecting against excessive peak currents in the power train, but you may see sub-harmonic oscillations if current limits happens at a duty cycle >50%. Again, this isn't a problem in itself - but it's generally considered undesirable.

    Adding the offset should have helped. This kind of instability could also be caused by an oscillation in the current sense signal - due to common mode currents in the transformer. I'd suggest a check of this and perhaps the customer could post an image of the CS waveform.

    Regards

    Colin

  • 0 in reply to Colin Gillmor
    TI__Expert 6730 points
    Thanks for the feedback. Customer has a follow up question on the asymmetrical operation:

    ..when I change the cap from 100n to 10n which is parallel with Ramp pin, the issue went away.

    Please help me understand this….

    Thanks!
  • 0 in reply to Allen Wachter
    TI__Mastermind 25570 points
    Hi
    If the customer is operating the controller in peak current mode then I'd think 100nF is too large and will filter the CS signal used by the PWM comparator to terminate the switching cycles. It may also be the case that the 100nF capacitor is not being discharged fully between switching cycles. To be honest, usually a 1k / 1nF RC filter is used to filter high frequency noise from this signal before it is applied to the CS pin. The amount of noise picked up by the CS signal is also a strong function of the PCB layout. Among other things the RC filter should be as close as possible to the CS pin.
    10nF may be ok but I'd suggest that 1k/1nF filter would be better.
    Can you send me a schematic please

    Regards
    Colin