In TPS3801 datasheet, Timing Diagram is shown as below.
When VDD is lower than 1.1V, the /RESET pin status is seems uncontrolled? Right?
Do we need to add a resistor with GND to keep /RESET low?
Thanks.
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In TPS3801 datasheet, Timing Diagram is shown as below.
When VDD is lower than 1.1V, the /RESET pin status is seems uncontrolled? Right?
Do we need to add a resistor with GND to keep /RESET low?
Thanks.