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LM3475: relationship between leading edge blanking time and SW node over/undershoot

Dongbao Zhou
Expert 4170 points
Part Number: LM3475

Hi there,

when i tested the pmlk with lm3475 on it, i didn't see any over/undershoot in SW node.

Would you mind tell me the reason? Because of the slow ramp up or shut down rate of Q1, or something else.

I was told the leading edge blanking time will attenuating the over or undershoot, is that correct?

thanks,

Dongbao

  • 0
    TI__Expert 5910 points
    Dongbao,
    Yes the leading edge blanking will reduce the overshoot. Typically when a sync fet is used the reverse recovery time of the internal body diode is also much worse than the schottky diode used on this board you are testing. Q1 pfet capacitances are also low on this board. All these factor into the SW pin waveform without spikes. Also check the bandwidth of your scope seting. Higher bandwidth scopes will show the spikes more easily.

    Regards,
    Mathew
  • 0 in reply to Mathew Jacob1
    TI__Expert 4170 points
    Mathew,

    Since the leading edge blanking time is 180ns, while the rising time of SW voltage is only about 60ns.
    Could you explain how does the leading edge blanking time reduce the overshoot?

    Regards,
    Dongbao
  • 0 in reply to Dongbao Zhou
    TI__Expert 5910 points
    Leading edge blanking and rise time of switch are independent. Rise time of switch happens after the blanking period. The gate drive strength and the fet capacitance determine the rise time. Using low capacitance fets and fast gate drive signals will cause ringing. In this case its a lower strenth gate drive and the fet internal gate resistance is also high slowing down the rise time.
  • 0 in reply to Mathew Jacob1
    TI__Expert 4170 points
    From my personal perspective, the leading edge blanking time are used to aviod undesired trigger during switching, undesired trigger will increase the overshoot, thus, leading edge blanking time helps to reduce overshoot indirectly. While slowing down the rise time and reducing the Q1 pfet capacitance will attentuate the overshoot directly.
    Is that correct?
  • 0 in reply to Dongbao Zhou
    TI__Expert 5910 points
    Yes this is correct.

    Regards,
    Mathew