• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 65 subscribers
  • Views 2732 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Gate drive circuit using a transformer

Gerhard Kreuzer
Expert 2600 points

Hi,

I found this article:

by Brian King and try to follow the schematics.

Unfortunately, it doesn't work as expected.

At small duty cycle values, the gate pulses for my power stage looking well, no Problem:

Signal names were selected according Brians schematic.

The waveform diagram in Brians article isn't correct, cause the positive and negative area of the pulses has to be the same to have sufficiant core reset.

I personally wondering, that the voltage Q2-D isn't rising to Vdd_drive, here about 17V, after the drive is switched off. As Brian describes his circuit and as I understand it, this voltage has to rise to Vdd-drive plus a forward biased Schottky Diode.

When I use longer duty cycles, some kind of flux walking set in. My core has 56Vµs and my drive voltage is 17V, so 3.2µs should be ok, my Problems starting at 2.4µs, here 3µs pulses were used.

The first cycle in this picture shows the saturated core, indicated by decreasing voltage at the end of the on phase. After switching off, the voltage at Q2_d rised imediately and we see, what Brian stated, so the core is properly reset?

The next cycle Shows the same behaviour as we have seen at smaller duty cycles before, and the next cycle also, but the effect is growing and than the core saturates again and then a cycle like the first follows.

Did flux walking take place?

Why does the circuit reset the core (more or less) only after the core saturates? Whats going on during the other cycles?

I tried to plot the voltage across the primary winding using the 'math' function of my scope:

Ok, the secondary voltage (= gate of my power stage Q1_G) just does what the (calculated) primary voltage do ==> the transformer is ok? The secondary voltage isn't disturbed by some malfunktion. The power stage works fine.

Did anybody have an idea whats going on here?

Thanks for helping.

With best regards

Gerhard

  • 0
    TI__Mastermind 31580 points
    Hi Gerhard

    We have copied our colleagues in the US for support on this post and you should see a response soon.

    Regards

    Peter
  • 0 in reply to Peter Meaney
    Expert 2600 points
    Thanks Peter,

    I changed the transistor today, but same result, so I have changed all parts over the days, no damaged part, must be something else.

    With best regards

    Gerhard
  • 0
    TI__Intellectual 2875 points

    After running a few simulations of your drive circuit, I think I see the problem.  Notice that the way we have the drive circuit configured, the gate capacitance is always connected across the secondary of the drive transformer.  After the drive signal goes low, we want the drive transformer to reset by allowing the primary voltage to reverse and hit the clamping diode connected to VDD.  However, we must charge the gate capacitance in the reverse direction in order to reach the VDD clamping voltage.  If the energy stored in the magnetizing inductance of the drive transformer is not larger than what is required to the charge the gate to -VDD, the transformer may not properly reset.  I suggest that you decouple the gate capacitance from the secondary of the gate drive transformer during turn-off, as shown in the attached drawing.  Another option would be to use a transformer with less inductance, but it must still withstand your Vus requirement.  Smaller FETs with less gate capacitance would help too, but this is probably not really an option for you.