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TPS7A63-Q1: About watchdog timeout after nWD_EN(Low->High->Low)

Part Number: TPS7A63-Q1

Hello Team,

When the High pulse of nWD_EN is set to 10us as shown below, the phenomenon that WD_FLT does not go Low after 8twd has occurred. Can you think of any cause?

By the way, setting the High pulse of nWD_EN to 100us will cause WD_FLT to go Low after 8 twd.

Best regards,
Kato

  • Hi Kato,

    Do you have any scope shots that show the behavior? It would be good to see nWD_EN, WD, and WD_FLT with both pulse times.

    Very Respectfully,
    Ryan
  • Hello Ryan-san,

    Because it is the waveform of my customer, I want to send it separately. Please tell me how to send it.

    Best regards,
    Kato

  • Hi Kato-san,

    Many times we are able to debug an application without requiring any sensitive information to the customer. In these cases we prefer to communicate openly on the forums so that anyone experiencing similar issues can benefit. In the event that you need to send a private message please review the following from the Learn E2E Blog:

    e2e.ti.com/.../3032.08-adding-friends-sending-private-messages

    Very Respectfully,
    Ryan
  • Hello Ryan-san,

    Please make a confirmation because I requested friendship.

    Best regards,
    Kato
  • Hi Kato-san,

    I apologize for the delay. This past weekend was a holiday for the US. I have accepted the friendship request.

    Very Respectfully,
    Ryan
  • Hello Ryan-san,

    My customers want answers as soon as possible. Please let me know when I can receive your reply.

    Best regards,
    Kato
  • Hi Kato-san,

    I apologize for the delay, I was attempting to reproduce your waveforms. I have replied to your private message.

    Very Respectfully,
    Ryan
  • Hi Kato-san,

    Per your request, I am also posting publicly that nWD_EN must be logic high for 50us or longer typically in order to ensure that the watchdog is disabled before the watchdog timeout. When the watchdog is re-enabled after the 50us, the watchdog will enter the first window of 8 x twd.

    Very Respectfully,
    Ryan
  • Hello Ryan-san,

    Is 50us considering temperature and voltage? Please tell me about the conditions for calculating that value.

    Best regards,
    Kato

  • Hi Kato-san,

    50us is considered typical. The conditions where this was measured was Vin = 14 V at 25C.

    Very Respectfully,
    Ryan
  • Hello Ryan-san,

    What is the reason why the high time of nWD_EN for disabling watchdog is not stipulated?

    And, my customer is asked the max value of the high time of nWD_EN for disabling watchdog considering the entire temperature range and voltage range. For example, is there a problem if there is twice the typical value(50us)?

    Best regards,
    Kato
  • Hi Kato-san,

    The intended application for this LDO is with the watchdog normally enabled. The watchdog enable is meant primarily to clear faults or disable the watchdog if it is not required rather than to avoid the watchdog fault from transitioning by preventing a time out (this is the intended function toggling the WD pin).

    There is no issue with leaving the watchdog disabled for longer periods of time from the device perspective.

    Very Respectfully,
    Ryan
  • Hello Ryan-san,

    Does the time to disable the watchdog by nWD_EN change with the value of Rosc? (50us(typ))
    I guess that the timing of the watchdog oscillator is related.
    If Yes, when Rosc=100kΩ±1%, how long time we should keep nWD_EN high to disable the watchdog? My customer is using Rosc=100kΩ±1%.
    The value ultimately requested by my customer is the maximum value of high-time of nWD_EN for disabling watchdog.
    Since there is no value in the data sheet, please tell me the value that is not guaranteed value but allowance on the design.

    Best regards,
    Kato
  • Hi Kato-san,

    You are correct that the minimum time that the watchdog must be disabled will change with the value of Rosc. I measured the 50us disable time on the bench for a Rosc of 100k since you had already provided the resistor size to me. In order to prevent WD_FLT from transitioning, you should disable the watchdog (WD_EN = logic high) for at least 50us when Rosc = 100k. Longer disable pulses are also okay.

    Could you help me understand why the customer wishes to disable the watchdog to prevent WD_FLT from transitioning rather than pulse WD in order to reset the watchdog timer?

    Very Respectfully,
    Ryan
  • Hello Ryan-san,

    50us is a typical value.(@Rosc=100kΩ±1%)
    In full temperature range and full voltage range, how long do you think should we keep nWD_EN=High at minimum to disable the watchdog?
    Is it enough that twice the 50us (=100us)?

    Best regards,
    Kato
  • Hi Kato-san,

    We have not characterized this operation over temperature; however, 100us is expected to be adequate. Again it is important to note that the intended method to reset the watchdog timer is to pulse WD rather than disable the watchdog. Can you help me understand why continuously disabling and enabling the watchdog is preferable for your application?

    Very Respectfully,
    Ryan
  • Hello Ryan-san,

    It is assumed that nWD_EN signal from MCU becomes high pulse in unexpected operation. My customers wanted to know how long high-time whether watchdog was reset or not reset.

    Best regards,
    Kato