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LP8860-Q1: PWM Resolution

Part Number: LP8860-Q1

Hello,

My customer would like to make sure whether Fig 17 is correct if I compare it with the specification on P9.




Fig 17 says that the 16bit resolution at the end of flow, however if I check the specifications on page 9, it seems maximum resolution is 13bit (typ).
Can you help me to understand how these numbers work?


Thank you for your support in advance.
Regards,
Ken

  • Hi Kenichiro-san,

    16 bit is total width of supported resolution at PWM output block not calculated from sample CLK freq/PWM freq.

    LP8860 has dithering function on PWM out up to 4 bit. So if actual PWM out resolution from sample CLK freq/PWM freq is 12 bit, it can still support 16 bit. If actual PWM resolution is 13 bit, max 16 bit resolution can be supported by using 3 bit dithering. For sure, input resolution should be 16 bit to get 16 bit output.

    Hope this helps,

  • Hi, Sung,

    Thank you for your prompt reply!I will consult with my customer and come back to you if further information is required.

    Regards,
    Ken

  • I'm glad to help you.

    I'm an apps engineer supporting Japanese customers, so you can also send me an email for quick response. I will be able to see E2E after it's assigned to me which may take longer to reply. My email is sungho.yoon@ti.com