TPS568215: Thermal management

Hi
1- Is the ground pins enough for heat spreading or should I use the SW pins too?
----Yes, SW should be helpful, but too width SW maybe will cause EMI issue. because sw is a PWM.
2- I reduced the ground and SW copper areas on the example board (so the board would not work electrically speaking). Is it OK for thermal simulation or it produces bogus (garbage in - garbage out)?
-----if the thermal model you build is accuracy, the thermal simulation should be believable, and there is webench available for this part, it is built based on EVM, can be for reference.
3- Is there some guideline about the minimum area to have efficient heat spreading? It would help me to reduce risk of having a sub par implementation of the supplies.
------acctually for thermal improvement from PCB, bascially ways just inculde enlarge copper area, add vias, make PCB copper thicker....
Also there is a layout guide at page25 in TPS568215 DS as bleow. you can refer to it.
• Recommend a four-layer or six-layer PCB for good thermal performance and with maximum ground plane. 3"
x 3", four-layer PCB with 2-oz. copper used as example.
• Recommend having equal caps on each side of the IC. Place them right across VIN as close as possible.
.......
.......
Also you can follow T_Juntcion=T_Ambient+ P_Diss× RθJA to do TJ pre-evalution.

Regards,
Yuchang

Hello Yuchang, thank you for your answer. My comments bellow yours.

----Yes, SW should be helpful, but too width SW maybe will cause EMI issue. because sw is a PWM.

That's great news, will facilitate things a lot.

-----if the thermal model you build is accuracy, the thermal simulation should be believable, and there is webench available for this part, it is built based on EVM, can be for reference.

To clear things up, I edited the copper areas of the board example in Webbench thermal simulator. I reduced copper area of the several layers (except the bottom one) to dimensions that looked reasonable for a real world design (the EVM is too big for most cases).

Original model with few changes (1oz on outer layers, 0.5oz inner layers, 50°C ambient temperature, no air flow), showing only the zoomed top layer:

Changed copper area (thus the board would be electrically broken):

Result

IC temperature increased 7°C (from 69 to 76°C @ 50°C ambient temperature) which is quite good IMO. The question is: is this result valid, considering the board would be electrically broken due to the way I changed the copper areas?

------acctually for thermal improvement from PCB, bascially ways just inculde enlarge copper area, add vias, make PCB copper thicker....

Unfortunately it is not doable (other than copper thicker) in most of real world designs where usually the power supply is part of a dense assembly.

Also there is a layout guide at page25 in TPS568215 DS as bleow. you can refer to it.
• Recommend a four-layer or six-layer PCB for good thermal performance and with maximum ground plane. 3"
x 3", four-layer PCB with 2-oz. copper used as example.
• Recommend having equal caps on each side of the IC. Place them right across VIN as close as possible.

I saw it. The layout is extremely clean. This chip is a little piece of art.

Best Regards.

Elder

Hi Elder,
First, reducing copper size gets higher thermal, this makes sense. and this should be valid for reference.
Also I think this should not cause electrically broken.
And also you can TJ-TA=Pdiss*RthjA to do TJ evaluation, and also add large copper, more vias to make PCB get better thermal performance.

Regards,
Yuchang