Dear TI engineer
My customer has question for TPS7A6350-Q1 enable pin level.
In D/S,
customer test result is
low level : about 1.35V, high level : about 1.7V
first of all, why is it so much better than the stated value?
is this level too high or low, even if it is referred to as variation for logic input?
they are asking for clarification of the exact reason.
Best regards.